• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.83-88
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• 2003

This paper analyses a fault operation due to the effect of miller capacitance, which severely influences the performance of the IPMs based on computer-aided simulations, and also it presents a good solution to solve that problem. A miller capacitance existed between gate and collect is very closely related to the stray capacitance formed between gate and emitter, and the value of gate resistor. These relationships are proved by the computer-aided simulation. Based on the PSpice simulation results, a customized IPM employing an auxiliary circuit is presented to minimize a fault operation. And it is compared to the standard IPM by the experimental waveform. As a result, it is verified that a customized IPM has a voltage margin to prevent a fault operation approx. 3 [V].

• Proceedings of the IEEK Conference
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• summer
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• pp.218-220
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• 2004

A new wide-band VCO topology using Miller capacitance is proposed. Contrary to conventional VCO using the Miller capacitance where the variable amplifier gain is negative, the proposed VCO uses both the negative and positive variable amplifier gain to enhance the frequency tuning range significantly. The proposed VCO is simulated using HSPICE. The simulations show that 410MHz and 220MHz frequency tuning range are obtained using the negative .and positive variable amplifier gain, respectively. The tuning range of the proposed VCO is $23\%$ of the center frequency(2.8GHz). The phase noise is -104dBc/Hz at 1MHz offset by simple model. The operating current is only 3.84mA at 2.5V power supply.

• Journal of IKEEE
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• v.16 no.4
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• pp.283-289
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• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.172-178
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• 2014

This paper presents a new model of the Miller effect. The new Miller effect model is obtained from the accurate AC gain which includes the effect of the output capacitance of the common-source (CS) amplifier. The new Miller effect model consists of the series connection of a capacitance and a parallel RC circuit, one at the input and the other at the output. The frequency response obtained by the new Miller effect model is equal to that obtained from the original circuit. Even though the new model is complicated, the 3-dB frequency can be easily estimated by using the open-circuit time constants method without the node analysis.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.11
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• pp.1053-1060
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• 2016

This paper proposes an adaptive equalizer with the digitally controlled active variable capacitor. An equalizing amplifier consists of a main amplifier and a source degeneration RC filter which is implemented using the digitally controlled active variable capacitor for area efficiency and linear loss compensation. The active capacitor changes its capacitance by the amplifier gain control, which is based on miller effect. In the simulated results, the proposed equalizer compensates the high frequency loss and extends the data eye width from 0.31 UI to 0.64 UI.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.482-491
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• 2012

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.1
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• pp.99-108
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• 2013

The high-voltage pulse generator is consist of transformers of fundamental wave and harmonic waves, and shunt capacitances. The pulse has the fundamental wave and the harmonic waves that have been increased as a series circuit by the transformers to make high voltage pulse. This paper shows that pulse generator circuit is analyzed using Miller's theorem and network theory(ABCD Matrix) and simulated in frequency and time domain using Matlab program. The output voltage of pulse were obtained to 2.5kHz, 1.8kV. Output pulse voltage increases as $L_m$ increases in low voltage circuit. In high voltage circuit, outer capacitors are related to frequency band pass characteristics.

• ETRI Journal
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• v.45 no.4
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• pp.690-703
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• 2023

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

• ETRI Journal
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• v.32 no.4
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• pp.520-529
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• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.130-137
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• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.