• 센서학회지
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• 제17권5호
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• pp.346-349
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• 2008

A metal-semiconductor-metal (MSM) ultraviolet (UV) photodetector (PD) is proposed as an effective UV sensing device for integration with a GaN n-channel MISFET on auto-doped p-type GaN grown on a silicon substrate. Due to the high hole barrier of the metal-p-GaN contact, the dark current density of the fabricated MSM PD was less than $3\;nA/cm^2$ at a bias of up to 5 V. Meanwhile, the UV/visible rejection ratio was 400 and the cutoff wavelength of the spectral responsivity was 365 nm. However, the UV/visible ratio was limited by the sub-bandgap response, which was attributed to defectrelated deep traps in the p-GaN layer of the MSM PD. In conclusion, an MSM PD has a high process compatibility with the n-channel GaN Schottky barrier MISFET fabrication process and epitaxy on a silicon substrate.

• 한국자기학회지
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• 제16권1호
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• pp.75-78
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• 2006

텅스턴-보론-카본질소 화합물 박막(W-B-C-N)을 만들기 위하여 박막내에 보론과 카본 그리고 질소의 불순물을 주입한 다음 결정구조를 조사하였으며, 이러한 박막의 식각 특성을 조사하기 위하여 고온에서 열처리한 다음 Cu박막을 W-B-C-N 박막위에 증착한 다음에 열처리하였고 여기에서 열적인 특성을 조사하였다. $1000\;{\AA}$의 박막을 RF magnetron sputtering방법을 이용하여 증착한 후에 박막의 전기적구조적인 특성을 측정하였으며, scratch test를 통해 박막의 결합력을 측정하였고, XRD측정을 통하여 결정성을 조사하였으며, 열처리한 후 etching을 하여 nomarski 현미경을 통하여 확산방지막의 안정성을 조사하였다. 이로부터 확산방지막내의 보론과 카본 질소 등의 불순물이 들어감에 따라 Cu가 Si 속으로 얼마나 들어가는가를 효과적으로 조사하였다. W-B-C-N 확산방지막의 역할은 $850^{\circ}C$까지 고온 열처리를 하는 경우에 Cu 원자가 Si 속으로 확산되어 나가는 것을 효과적으로 방지하는 것을 알 수 있었다. 텅스텐-보론-카본질소 화합물 박막의 비저항은 질소 가스의 유량비를 조절함으로써 쉽게 조절할 수 있었으며, 텅스텐-보론-카본-질소 화합물 박막은 Cu 확산방지막으로 적용했을 때 적절한 질소 농도가 들어간 확산방지막에서는 효과적으로 Cu의 확산을 방지하는 것을 알 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.86-86
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• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2004년도 춘계학술대회 발표 논문집
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• pp.159-162
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• 2004

Problems of overlap errors and sidelobe printing by the design rule reduction in the lithography process using attenuated phase-shifting masks(attPSM) have been serious. Overlap errors and sidelobes can be simultaneously solved by the rule-based correction using scattering bars with the rules extracted from test patterns. Process parameters affecting the attPSM lithography simulation have been determined by the fitting method to the process data. Overlap errors have been solved applying the correction rules to the metal patterns overlapped with contact/via. Moreover, the optimal insertion rule of the scattering bars has made it possible to suppress the sidelobes and to get additional pattern fidelity at the same time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.310-313
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• 2000

In this study, the Au/Ni and Au/Ni/Si/Ni layers prepared by electron beam evaporation were used to form ohmic contacts on p-type GaN. Before rapid thermal annealing, the current-voltage(I-V) characteristic of Au/Ni and Au/Ni/Si/Ni contact on p-type GaN film shows non-ohmic behavior. A Specific contact resistance as 3.4$\times$10$^{-4}$ Ω-$\textrm{cm}^2$ was obtained after 45$0^{\circ}C$-RTA. The Schottky barrier height reduction may be attributed to the presence of Ga-Ni and Ga-Au compounds, such as Ga$_4$Ni$_3$, Ga$_4$Ni$_3$, and GaAu$_2$ at the metal - semiconductor interface. The mixing behaviors of both Ni and Au have been studied by using X-ray photoelectron spectroscopy. In addition, X-ray diffraction measurements indicate that the Ni$_3$N, NiGa$_4$, Ni$_2$Si, and Ni$_3$Si$_2$ Compounds were formed at the metal-semiconductor interface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.300-308
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• 2010

This paper describes the development of a low-power electrocardiogram (ECG) touch sensor intended for the use with two dry metal electrodes. An equivalent ECG extraction circuit model encountered in a ground-free two-electrode configuration is investigated for an optimal sensor read-out circuit design criteria. From the equivalent circuit model, (1) maximum sensor resolution is derived based on the electrode's background thermal noise, which originates from high electrode-skin contact impedance, together with the input referred noise of instrumentation amplifier (IA), (2) 60 Hz electrostatic coupling from mains and motion artifact are also considered to determine minimum requirement of common mode rejection ratio (CMRR) and input impedance of IA. A dedicated ECG read-out front end incorporating chopping scheme is introduced to provide an input referred circuit noise of 1.3 ${\mu}V_{rms}$ over 0.5 Hz ~ 200 Hz, CMRR of IA > 100 dB, sensor resolution of 7 bits, and dissipating only 36 ${\mu}W$. Together with 8 bits synchronous successive approximation register (SAR) ADC, the sensor IC chip is implemented in 0.18 ${\mu}m$ CMOS technology and integrated on a 5 cm $\times$ 8 cm PCB with two copper patterned electrodes. With the help of proposed touch sensor, ECG signal containing QRS complex and P, T waves are successfully extracted by simply touching the electrodes with two thumbs.

• ETRI Journal
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• 제35권4호
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• pp.571-577
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• 2013

The fabrication of a thin-film transistor backplane and a liquid-crystal display using printing processes can eliminate the need for photolithography and offers the potential to reduce the manufacturing costs. In this study, we prepare contact via structures through a poly(methyl methacrylate) polymer insulator layer using inkjet printing. When droplets of silver ink composed of a polymer solvent are placed onto the polymer insulator and annealed at high temperatures, the silver ink penetrates the interior of the polymer and generates conducting paths between the top and bottom metal lines through the partial dissolution and swelling of the polymer. The electrical property of various contact via-hole interconnections is investigated using a semiconductor characterization system.

• 한국산업융합학회 논문집
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• 제10권3호
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• pp.179-185
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• 2007

Quartz glass are used in semiconductor industries as the reaction furnace, wafer carrier and accessaries. During the process the quartz glass received compression by direct contact with other quartz glass ware and metal as the form of weight itself and vacuum pressure and fatigue by vibrations caused by process. Even as the other ceramic materials quartz glass have high compressive strength but often there happened crack and breakage of quartz glass resulted in a great damage in the process. In this paper investigation will be carried out on fracture behavior of quartz glass under local load to give guideline to prevent unintended fracture of quartz glass.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.12-17
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• 2004

The body-tied FinFETs (bulk FinFETs) implemented on bulk Si substrate were characterized through 3-dimensional device simulation. By controlling the doping profile along the vertical fin body, the bulk FinFETs can be scaled down to sub-30 nm. Device characteristics with the body shape were also shown. At a contact resistivity of $1{\times}10^{-7}\;{\Omega}\;cm^2$, the device with side metal contact of fin source/drain showed higher drain current by about two. The C-V results were also shown for the first time.

• 한국전기전자재료학회논문지
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• 제25권3호
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• pp.236-240
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• 2012

Limiting thermal exposure time using rapid thermal processing(RTP) has emerged as promising simplified process for manufacturing of solar cell in a continuous way. This paper reports the simplification of co-firing using RTP. Actual temperature profile for co-firing after screen printing is a key issue for high-quality metal-semiconductor contact. The plateau time during the firing process were varied at $450^{\circ}C$ for 10~16 sec. Glass frit in Ag paste etch anti-reflection layer with plateau time. Glass frit in Ag paste is important for the Ag/Si contact formation and performances of crystalline Si solar cell. We achieved 17.14% efficiency with optimum conditions.