• ETRI Journal
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• v.34 no.3
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• ETRI Journal
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• v.33 no.6
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• pp.904-913
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.

• ETRI Journal
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• v.32 no.4
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• Journal of the Korean Society for Heat Treatment
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• v.27 no.2
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• pp.59-64
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• 2014

Cu-Al-Mn shape memory alloys of a variety of composition were characterized in terms of shape memory properties and cold workability. Cold workability tested by cold rolling indicated that the alloys solution treated in the ${\alpha}+{\beta}$ region have a higher ductility than those solution treated in the ${\beta}$ region. Also it is known that cold workability increased with the decrease in Al content in the ${\beta}$ region. This seems to be resulted from the fact that Mn addition causes to expand ${\beta}$ region toward lower Al content and lower order-disorder transition temperature, consequently, ${\beta}$ of excellent workability being frozen even at room temperature. Experimental results regarding shape memory showed that the properties were better with a higher Al contents at a given Mn content, which is closely related with martensitic transformation. It is also shown that super elasticity limit was enhanced with decrease in the yield strength of alloys because a lower yield strength seems to initiates slip at the lower applied stress.

• Journal of Mechanical Science and Technology
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• v.19 no.7
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• pp.1460-1468
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• 2005

Two possible shape memory processes, austenite to detwinned martensite transformation and twinned martensite to detwinned martensite transformation of a shape memory alloy have been modeled and examined. Eshelby's equivalent inclusion method with Mori-Tanaka's mean field theory is used for modeling of the shape memory processes of TiNi shape memory alloy reinforced aluminum matrix composite. The shape memory amount of shape memory alloy, plastic strain and residual stress in the matrix are computed and compared for the two processes. It is shown that the shape memory amount shows differences in a small prestrain region, but the plastic strain and the residual stress in the matrix show differences in the whole prestrain region. The shape memory process with initially martensitic state of the shape memory alloy would be favorable to the increase in the yield stress of the composite owing to the large compressive residual stress and plastic strain in the matrix.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.38-45
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• 2014

This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• Korean Journal of Materials Research
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• v.9 no.4
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• pp.419-427
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• 1999

TiNi shape memory alloy was shape memory heat-treated and investigated its mechanical properties with the variation of prestrain. Also 6061 Al matrix composites with TiNi shape memory alloy fiber as reinforcement have been fabricated by Permanent Mold Casting to investigate the microstructures and interface properties. Yield stress of TiNi wire was the most high in the case of before heat-treatment and then decreased as increasing heat-treatment time. In each heat-treatment condition, the yield stress of TiNi wire was not changed with increasing the amount of prestrain. The interface bonding of TiNi/6061Al composite was fine. There was a 2$\mu\textrm{m}$ thickness of diffusion reaction layer at the interface. We could find out that this diffusion reaction layer was made by the mutual diffusion. The diffusion rate from Al base to TiNi wire was faster than that of reverse diffusion and the amount of the diffusion was also a little more than that of reverse.