• Title/Summary/Keyword: memory process

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Design of Zero-Layer FTP Memory IP (PMIC용 Zero Layer FTP Memory IP 설계)

  • Ha, Yoongyu;Jin, Hongzhou;Ha, Panbong;Kim, Younghee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.6
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    • pp.742-750
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    • 2018
  • In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

Memory Injection Technique and Injected DLL Analysis Technique in Windows Environment (윈도우 환경에서의 메모리 인젝션 기술과 인젝션 된 DLL 분석 기술)

  • Hwang, Hyun-Uk;Chae, Jong-Ho;Yun, Young-Tae
    • Convergence Security Journal
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    • v.6 no.3
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    • pp.59-67
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    • 2006
  • Recently the Personal Computer hacking and game hacking for the purpose of gaining an economic profit is increased in Windows system. Malicious code often uses methods which inject dll or code into memory in target process for using covert channel for communicating among them, bypassing secure products like personal firewalls and obtaining sensitive information in system. This paper analyzes the technique for injecting and executing code into memory area in target process. In addition, this analyzes the PE format and IMPORT table for extracting injected dll in running process in affected system and describes a method for extracting and analyzing explicitly loaded dll files related with running process. This technique is useful for finding and analyzing infected processes in affected system.

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Implementation of Integrated CPU-GPU for Efficient Uniform Memory Access Method and Verification System (CPU-GPU간 긴밀성을 위한 효율적인 공유메모리 접근 방법과 검증 시스템 구현)

  • Park, Hyun-moon;Kwon, Jinsan;Hwang, Tae-ho;Kim, Dong-Sun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.2
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    • pp.57-65
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    • 2016
  • In this paper, we propose a system for efficient use of shared memory between CPU and GPU. The system, called Fusion Architecture, assures consistency of the shared memory and minimizes cache misses that frequently occurs on Heterogeneous System Architecture or Unified Virtual Memory based systems. It also maximizes the performance for memory intensive jobs by efficient allocation of GPU cores. To test between architectures on various scenarios, we introduce the Fusion Architecture Analyzer, which compares OpenMP, OpenCL, CUDA, and the proposed architecture in terms of memory overhead and process time. As a result, Proposed fusion architectures show that the Fusion Architecture runs benchmarks 55% faster and reduces memory overheads by 220% in average.

The Effect of Memory Load on Maintenance in Face and Spatial Working Memory: An Event-Related fMRI Study (기억부하가 얼굴과 공간 작업기억의 유지에 미치는 효과: 사건유관 fMRI 연구)

  • Kim, Jung-Hee;Jeong, Gwang-Woo;Kang, Heoung-Keun;Lee, Moo-Suk;Park, Tae-Jin
    • Korean Journal of Cognitive Science
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    • v.21 no.2
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    • pp.359-386
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    • 2010
  • In order to evaluate the domain-specific model and process-specific model of spatial and nonspatial working memory (WM), this study manipulated the memory load of the delayed response task and examined how the neural correlates of memory load effect was influenced by the stimulus domain (face and location) at the maintenance stage of WM using an event-related fMRI experiment. One or three face stimuli were presented as target stimuli and participants were asked to maintain the face itself (face WM) or the location of face stimuli (spatial WM). The results of recognition judgment accuracy showed no difference between face WM and spatial WM, and showed equivalent memory load effects of both WM. As a result of brian image analysis, memory load effect at maintenance stage showed that inferior, middle, and superior PFC were recruited by both face WM and spatial WM, and showed that VLPFC was the commonly activated area by both WM, supporting functional specialization of PFC by process components of WM. This study provides evidence for process-specific model in which maintenance of WM is associated with VLPFC.

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Technology of the next generation low power memory system

  • Cho, Doosan
    • International Journal of Internet, Broadcasting and Communication
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    • v.10 no.4
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    • pp.6-11
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    • 2018
  • As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

MRAM Technology for High Density Memory Application

  • Kim, Chang-Shuk;Jang, In-Woo;Lee, Kye-Nam;Lee, Seaung-Suk;Park, Sung-Hyung;Park, Gun-Sook;Ban, Geun-Do;Park, Young-Jin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.185-196
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    • 2002
  • MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

The Design of the Shared Memory in the Dual Core System (Dual Core 시스템에서 Shared Memory 기능 설계)

  • Jang, Seung-Ju;Lee, Gwang-Yong;Kim, Jae-Myeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.8
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    • pp.1448-1455
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    • 2008
  • This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory in this paper among big two branches of Shared Memory which are SVR in a kernel step format. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting design plan of share memory facility in Dual Core system is enhancing the performance in existing unity processor system as a dual core practical use. We attempt a performance enhance in each CPU for each process which uses a share memory.

A Study on the Characteristics and Programming Conditions of the Scaled SONOSFET NVSM for Flash Memory (플래시메모리를 위한 Scaled SONOSFET NVSM의 프로그래밍 조건과 특성에 관한 연구)

  • 박희정;박승진;남동우;김병철;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.11
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    • pp.914-920
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    • 2000
  • When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

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Organic-Inorganic Nanohybrid Structure for Flexible Nonvolatile Memory Thin-Film Transistor

  • Yun, Gwan-Hyeok;Kalode, Pranav;Seong, Myeong-Mo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.118-118
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    • 2011
  • The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

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