• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.339-345
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• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.2
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• pp.105-112
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• 2017

In order to satisfy the diffusion of multimedia service in mobile communication and the demand for high-speed communication, it is essential to modify and improve high efficiency, wideband and nonlinear characteristic of multiband power amplifier. This research is designed to implement a single-stub matching circuit as a 2nd harmonic one that meets conditions of the Class-J power amplifier. Low characteristic impedance of the single-stub line is necessary to suit conditions of wideband Class-J. This research uses ceramic substrates having high permittivity to implement the single-stub line with low characteristic impedance, which eventually results in an amplifier satisfying the output impedance terms of Class-J in wideband frequency range. This result attributes to use of GaN HEMT packaged with a 2nd harmonic matching circuit and external fundamental circuit. The measurement results of the Class-J amplifier confirms the following characteristics: more than output power of 50 W(47 dBm) in bandwidth of 1.8~2.7 GHz(0.9GHz), maximum drain efficiency of 72.6 %, and maximum PAE characteristic of 66.5 %.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.104-110
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• 2019

In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.215-216
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• 2008

In this paper, we describe a UHF-band CMOS fractional-N frequency synthesizer using a ring - type VCO. It has been designed using $0.18{\m}m$ CMOS technology. First, The newly designed charge-pump circuit includes an OTA for matching between the upper current and the lower current In addition, a ring - type VCO is also used for small chip sire. The simulation results show that the designed circuit has a phase noise of -109.53dBc/Hz at 1MHz offset and consumes 19.4mA from a 1.8V supply. The lock time is less than 30usec and the chip size is $0.45mm{\times}0.5mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.276-283
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• 2003

In this paper, a 2-stage power amplifier(PA) for IMT-2000 handset has been designed and fabricated using SiGe HBT, which has excellent frequency characteristics and linearity, to reduce size and weight instead of existing linearization techniques. DC I-V characteristics and S-parameter of SiGe HBT were simulated by Agilent circuit simulator(ADS), with large signal Gummel-Poon nonlinear circuit model. Then the output and interstage matching circuits were designed to satisfy the high power condition and the high gain condition, respectively. The experimental results showed output power of 27.1dBm and ACLR of 20dB, PAE of 34%, and linear power gain of 18.9dB over frequency ranges from 1920MHz to 1980MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.5
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• pp.657-662
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• 2013

A size-reduced high frequency mixer designed by adopting artificial dielectric substrate is described in this work. The artificial dielectric substrate is composed by stacking the lower substrate in which a lot of metalized via-holes exist, and upper substrate on which microstrip lines are realized. The effective dielectric constant increases due to the inserted lots of via-holes, and this may be applied to size-reduction of high frequency circuits. In this work, in order to present an application example of size-reduction for active high frequency circuits using the artificial dielectric substrate, a 8GHz single gate mixer is miniaturized and measured. It is described that the basic circuit elements for mixers such as hybrid, low pass filter, and matching networks can be replaced by the artificial dielectric substrate for size-reduction. The final mixer has 55% of size compared to the normal one. The measured average conversion gain is around 3dB which is almost similar result as the normal circuit.