• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• ETRI Journal
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• v.24 no.6
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1221-1229
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• 1996

This paper proposes a heuristic algorithm for low power implementation of combinational circuits. Selecting an input variable for a given function, the proposed algorithm performs Shannon exansion with respect to the variable to reduce the number of gates in the subcircuit realizing the coffactor function, reducting the power dissipation of the implemented circuit. experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating the circuits consuming the power 48.9% less on the average, when compared to the previous algorithm based on precomputation logic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.2
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• pp.102-107
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• 2005

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.46-58
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• 1998

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.221-225
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• 2014

Low power RF devices, such as RFID and Zigbee, are important for ubiquitous sensing. These devices, however, are powered by portable energy sources, such as batteries, which limits their use. To mitigate this problem, this study developed RF energy harvesting with W-CDMA for a low power RF device. Diodes are required with a low turn on voltage because the diode threshold is larger than the received peak voltage of the rectifying antenna (rectenna). Therefore, a Schottky diode HSMS-286 was used. A prototype of RF energy harvesting device showed the maximum gain of 5.8dBi for the W-CDMA signal. The 16 patch antennas were manufactured with a 10 dielectric constant PTFT board. In low power RF devices, the transmitter requires a step-up voltage of 2.5~5V with up to 35 mA. To meet this requirement, the Texas Instruments TPS61220 was used as a low input voltage step-up converter. From the evaluated result, the achievable incident power of the rectenna at 926mV to operate Zigbee can be obtained within a distance of 12m.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.159-162
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• 2007

Comparative study on a low cost sustaining driver with single and dual path energy recovery circuits for plasma display panels (PDPs) is shown in this paper. The cost of PDPs has been still high and about half of the cost has been occupied by driving circuit. A simple sustaining driver is proposed to reduce the cost and size of driving circuit. The proposed driver has small number of devices and reactive components and there are two methods for charging and discharging PDPs such as single and dual path energy recovery circuits. A comparative research on two-types of energy recovery path is practiced to evaluate performance. As a result, the dual energy recovery path circuit has low power consumption, low surge current and high performance. To verify those results, experiment will be shown with 42-inch HD panel.