• 제목/요약/키워드: low resistance contact formation

검색결과 56건 처리시간 0.026초

Ni/Cu 금속전극 태양전지의 Ni electroless plating에 관한 연구 (The Research of Ni Electroless Plating for Ni/Cu Front Metal Solar Cells)

  • 이재두;김민정;권혁용;이수홍
    • 한국전기전자재료학회논문지
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    • 제24권4호
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    • pp.328-332
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    • 2011
  • The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surface. One of the front metal contacts is Ni/Cu plating that it is available to simply and inexpensive production to apply mass production. Ni is shown to be a suitable barrier to Cu diffusion into the silicon. The process of Ni electroless plating on front silicon surface is performed using a chemical bath. Additives and buffer agents such as ammonium chloride is added to maintain the stability and pH control of the bath. Ni deposition rate is found to vary with temperature, time, utilization of bath. The experimental result shown that Ni layer by SEM (scanning electron microscopy) and EDX analysis. Finally, plated Ni/Cu contact solar cell result in an efficiency of 17.69% on $2{\times}2\;cm^2$, Cz wafer.

Si 기판 GaSb 기반 p-채널 HEMT 제작을 위한 오믹 접촉 및 식각 공정에 관한 연구 (A Study on the Ohmic Contacts and Etching Processes for the Fabrication of GaSb-based p-channel HEMT on Si Substrate)

  • 윤대근;윤종원;고광만;오재응;이재성
    • 전기전자학회논문지
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    • 제13권4호
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    • pp.23-27
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    • 2009
  • 실리콘 기판 상에 MBE (molecular beam epitaxy)로 형성된 GaSb 기반 p-channel HEMT 소자를 제작하기 위하여 오믹 접촉 형성 공정과 식각 공정을 연구하였다. 먼저 각 소자의 절연을 위한 메사 식각 공정 연구를 수행하였으며, HF기반의 습식 식각 공정과 ICP(inductively coupled plasma)를 이용한 건식 식각 공정이 모두 사용되었다. 이와 함께 소스/드레인 영역 형성을 위한 오믹 접촉 형성 공정에 관한 연구를 진행하였으며 Ge/Au/Ni/Au 금속층 및 $300^{\circ}C$ 60초 RTA공정을 통해 $0.683\;{\Omega}mm$의 접촉 저항을 얻을 수 있었다. 더불어 HEMT 소자의 게이트 형성을 위한 게이트 리세스 공정을 AZ300 현상액과 citric산 기반의 습식 식각을 이용하여 연구하였으며, citric산의 경우 소자 구조에서 캡으로 사용된 GaSb와 베리어로 사용된 AlGaSb사이에서 높은 식각 선택비를 보였다.

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표면조도 특성에 따른 저항 점 용접성 평가 및 너깃 형성 고찰 (Evaluation on Resistance Spot Weldability and Nugget Formation of Surface Roughness Treated Steel Sheet)

  • 김기홍;최영민;김영석;임영목;유지훈;강남현;박영도
    • Journal of Welding and Joining
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    • 제26권5호
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    • pp.79-89
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    • 2008
  • With the increased use of surface textured steel sheet in body-in-white assembly, resistance spot weldability of these steels is considered to be an important subject. This study evaluated nugget formation and weldability by measuring dynamic resistance with various weld pressure, current, and weld time for steel sheet with two different surface roughnesses. The surface roughness for T-H steel ($R_{a}=1.70\;{\mu}m$) was higher than that for T-L steel ($R_{a}=1.33\;{\mu}m$), and resulted in increased contact resistance and heating for T-H steel spot welding. Therefore, at low weld current and weld cycle ranges, the T-H steel showed better weldability over the T-L steel. The evaluations of weld interface showed that the fusion zone in the T-H steel sheet was continuous in contrast to discontinuous fusion zone for T-L steel sheet at the same welding conditions. A comparison of dynamic resistance and tensile-shear strength (TSS) between T-H and T-L steel sheet suggested that high surface roughness provided larger heating at early cycle of welding and larger TSS.

Textured 표면을 갖는 에피텍셜 베이스 실리콘 태양전지 (Textured Surface Epitaxial Base Silicon Solar Cell)

  • 장지근;임용규;정진철
    • 마이크로전자및패키징학회지
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    • 제10권2호
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    • pp.33-37
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    • 2003
  • Si 태양전지의 효율 개선을 위해 textured 표면을 갖는 에피텍셜 베이스 전지(TSEB)를 제작하고 이의 전기광학적 특성을 조사하였다. 제작된 전지는 AM-1 100 mW/$cm^2$ 입사광 아래에서 개방전압이 0.62 V로, 단락전류가 40 mA로, 충실도가 0.7, 전력변환 효율이 16%로 나타났다. 본 연구에서 제안된 전지는 $P^-/P^+$ 에피구조에 의한 광흡수 영역에서 캐리어의 드리프트 이동과 효과적 배면전계의 형성, 그리고 buried contact을 통한 낮은 직렬저항 등으로 인해 고효율 Si 태양전지의 제작에 적합한 구조로 판단된다.

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Integration Technologies for 3D Systems

  • Ramm, P.;Klumpp, A.;Wieland, R.;Merkel, R.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2003년도 International Symposium
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    • pp.261-278
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    • 2003
  • Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

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N형 고분자 반도체의 전하주입 특성 향상을 통한 저전압 유기전계효과트랜지스터 특성 연구 (Low-Voltage Operating N-type Organic Field-Effect Transistors by Charge Injection Engineering of Polymer Semiconductors and Bi-Layered Gate Dielectrics)

  • 문지훈;백강준
    • 한국전기전자재료학회논문지
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    • 제30권10호
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    • pp.665-671
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    • 2017
  • Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

단결정 실리콘 기판에 이온주입된 불순물이 $TaSi_2$형성에 미치는 영향 (The effect of impurities implanted single-Si substrates on the formation of $TaSi_2$)

  • 조현춘;최진석;고철기;백수현
    • 한국재료학회지
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    • 제1권1호
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    • pp.17-22
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    • 1991
  • 불순물이 주입된 실리콘 기판에 500 두께의 탄탈륨 박막을 증착한 후 실리사이드를 형성시키기 위해 아르곤 분위기에서 급속열처리(RTA)률 하였다. 형성된 $TaSi_2$와 불순물의 거동은 XRD, SEM, 4-point probe, HP4145와 SIMS로 조사하였다. 불순물의 종류에 관계없이 $TaSi_2$는 RTA 온도가 $800^{\circ}C$일때 형성되기 시작하였으며 $1000^{\circ}C$이상에서 증착된 Ta가 전부 $TaSi_2$로 상 전이가 일어났다. 또한 $TaSi_2/P^+$영역에 대한 접촉저항간은 contact size가 $0.9{\times}0.9({\mu}{m^2}$)일때 $22{\Omega}$ 낮은값을 가졌으며 이온 주입된 불순물은 RTA처리시 형성된 $TaSi_2$층으로 out-diffusion이 일어났다.

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시뮬레이션을 이용한 780MPa급 강재의 판재 조합에 따른 저항 점 용접의 로브곡선 특성 분석 (Lobe Curve Characteristic Analysis of Resistance Spot Welding for Sheet Combination of 780MPa Steel Sheet Using Simulation)

  • 손창석;박영환
    • Journal of Welding and Joining
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    • 제30권6호
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    • pp.68-73
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    • 2012
  • Nowadays, car manufacturers tried to improve automotive fuel efficiency, and applied many high strength steels such as AHSS or UHSS to car bodies. Therefore, the number of steel combinations for the resistance spot welding are dramatically increased and the need for weldability evaluation of these combinations are also required. In this study, we suggest the lobe curve using FEM simulations for DP780 steel with 1.0t, 1.4t. The lobe curves which could expressed weldablity and optimal welding condition were obtained according to 6 steel combinations. There were two combinations for same steel sheet which were DP780 1.0t, DP780 1.4t. Dissimilar steel sheet combination with different thickness was 1.0t and 1.4t of DP780. Different steel combinations were DP780 1.0t and SPRC440 1.0t, and DP780 1.0t and DP590 1.0t. Finally dissimilar combinations was and DP780 1.0t and DP590 1.4t. The trend of low boundary and high boundary variation of lobe curve were analyzed with a viewpoint of the contact resistance and the heat input.

섬유보강 규산칼슘수화물 경화체의 미세조직과 기계적 특성 (The Microstructure and Mechanical Properties of Fiber Reinforced Calcium Silicate Hydrates)

  • 엄태선;최상흘
    • 한국세라믹학회지
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    • 제34권5호
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    • pp.491-499
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    • 1997
  • High flexible lightweight composites containing tobermorite as a main mineral is produced using various amorphous silicates, lime, cement and fibers. Here, Mechanical properties of the composites were studied by observing microstructures of hydrates and fibers. Amorphous silicates having better hydraulicity retarded the crystallization of tobermorite due to better formation of C-S-H gel in water bath curing, but, difficult conversion from C-S-H gel to tobermorite in hydrothermal reaction. In the low molar ratio of CaO/SiO2 (0.67), faster crystalization was observed dued to more impurities such as Al2O3 alkali, resulting in improving mechanical properties due to small crystal size and many contact points. It was identified that a lot of calcium silicate hydates formed at surface of pulps increase bonding strength and the crack-resistance of matrix in the composites, but decrease hardness and compressive strength. The choice of amorpous silicates having better hydraulicity, low CaO/SiO2 adding each fibers bellow about 5% in the raw mixs and lower molding pressure should be needed at improve mechanical properties of composites.

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차세대 전력 스위치용 1.5 kV급 GaN 쇼트키 장벽 다이오드 (1.5 kV GaN Schottky Barrier Diode for Next-Generation Power Switches)

  • 하민우
    • 전기학회논문지
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    • 제61권11호
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    • pp.1646-1649
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    • 2012
  • The $O_2$ annealing technique has considerably suppressed the leakage current of GaN power devices, but this forms NiO at Ni-based Schottky contact with increasing on-resistance. The purpose of the present study was to fabricate 1.5 kV GaN Schottky barrier diodes by improving $O_2$-annealing process and GaN buffer. The proposed $O_2$ annealing performed after alloying ohmic contacts in order to avoid NiO construction. The ohmic contact resistance ($R_C$) was degraded from 0.43 to $3.42{\Omega}-mm$ after $O_2$ annealing at $800^{\circ}C$. We can decrease RC by lowering temperature of $O_2$ annealing. The isolation resistance of test structure which indicated the surface and buffer leakage current was significantly increased from $2.43{\times}10^7$ to $1.32{\times}10^{13}{\Omega}$ due to $O_2$ annealing. The improvement of isolation resistance can be caused by formation of group-III oxides on the surface. The leakage current of GaN Schottky barrier diode was also suppressed from $2.38{\times}10^{-5}$ to $1.68{\times}10^{-7}$ A/mm at -100 V by $O_2$ annealing. The GaN Schottky barrier diodes achieved the high breakdown voltage of 700, 1400, and 1530 V at the anode-cathode distance of 5, 10, and $20{\mu}m$, respectively. The optimized $O_2$ annealing and $4{\mu}m$-thick C-doped GaN buffer obtained the high breakdown voltage at short drift length. The proposed $O_2$ annealing is suitable for next-generation GaN power switches due to the simple process and the low the leakage current.