• ETRI Journal
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• 제25권5호
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• 한국태양에너지학회 논문집
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• 제31권4호
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• pp.19-26
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• 2011

We are carried out power performance testing for 3MW wind turbine system at Je-ju wind turbine testing Site and analyzed measured data which was stored through monitoring system. In this paper, we described the power performance testing results and analyzed an uncertainty of measured data sets. The power curve with measured power data is closely coincide with designed power curve except for the low wind speed sections(4m/s~7m/s) and the annual energy production which is given Ray leigh distribution was included with 1.5~5.9% of uncertainty in the wind speed region as 4~11m/s. Although the deviation of curve between measured power and designed power is high, the difference of annual energy production is low in the low wind speed region.

• 한국콘텐츠학회논문지
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• 제5권1호
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• pp.229-236
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• 2005

System-On-a-Chip(SOC)을 테스트하는 동안에 요구되는 테스트 시간과 전력소모는 SOC내의 IP 코어의 개수가 증가함에 따라서 매우 중요하게 되었다. 본 논문에서는 수정된 스캔 래치 재배열을 사용하여 scan-in 전력소모와 테스트 데이터의 양을 줄일 수 있는 새로운 알고리즘을 제안한다. 스캔 벡터 내의 해밍거리를 최소화하도록 스캔 래치 재배열을 적용하였으며 스캔 래치 재배열을 하는 동안에 스캔 벡터 내에 존재하는 don't care 입력을 할당하여 저전력 및 테스트 데이터 압축을 하였으며 ISCAS 89 벤치마크 외호에 적용하여 모든 경우에 있어서 테스트 데이터를 압축하고 저전력 스캔 테스팅을 구현하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.961-963
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• 2000

Most of the application standard of the low-voltage devices have applied one the IEC standard another the UL standard. European union applied the IEC60947-1 standard has not exceed 1000V a.c. or 1500V d.c.. Therefore. it is necessary to the low-voltage device has expended for rated operational voltage with our products. The export of European market shall be made for the CE-Marking in accordance with IEC60947-1 ( Low-voltage switchgear and controlgear). We shall be considered for the requirement with the IEC standard. In this time to study for power supply system at EU ( European union. At that time for design and development in order to the construction and test method among the study for the rated insulation voltage at less then 690V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.253-257
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• 2003

This paper presents the Development of Switching Power Supply for testing communication equipment. The communication equipment need many kinds of voltage(-48V,27V,12V,5V,3.3V), and in case of low voltage needs large current($10{\sim}20A$). The previous Linear Power Supply was very heavy, has low efficiency and poor power-factor for testing communication equipment. This development has good efficiency and high power-factor using switch mode power supply technique. This Development of Switching Power Supply is composed of eight converters. The principles of operation, feature, and design considerations are illustrated and verified through the experiment with 600W prototype.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권3호
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• pp.1393-1405
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• 2017

It is well known that duty-cycling control by dynamically adjusting the polling interval according to the traffic loads can effectively achieve power saving in wireless sensor networks. Thus, there has been a significant research effort in developing polling interval adaptation schemes. Especially, Dynamic Low Power Listening (DLPL) scheme is one of the most widely adopted open-looping polling interval adaptation techniques in wireless sensor networks. In DLPL scheme, if consecutive idle (busy) samplings reach a given fixed threshold, the polling interval is increased (decreased). However, due to the trial-and-error based approach, it may significantly deteriorate the system performance depending on given threshold parameters. In this paper, we propose a novel DLPL scheme, called SDL (Sequential hypothesis testing based Dynamic LPL), which employs sequential hypothesis testing to decide whether to change the polling interval conforming to various traffic conditions. Simulation results show that SDL achieves substantial power saving over state-of-the-art DLPL schemes.

• 대한전자공학회논문지SD
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• 제39권12호
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• pp.1045-1054
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• 2002

System-On-a-Chip(SOC)에 대하여 테스트 데이터 압축 및 저전력 스캔테스팅에 대한 새로운 알고리즘을 제안하였다. 스캔벡터내의 don't care 입력들을 저전력이 되도록 적절하게 값을 할당하였고 높은 압축율을 갖도록 적응적 인코딩을 적용하였다. 또한 스캔체인에 입력되는 동안 소모되는 scan-in 전력소모를 최소화하도록 스캔벡터의 입력 방향을 결정하였다. ISCAS 89 벤치마크 회로에 대하여 실험한 결과는 평균전력 소모는 약 12% 감소되었고 압축율은 약 60%가 향상됨을 보였다.

• 대한전자공학회논문지SD
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• 제41권9호
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• pp.85-95
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• 2004

최근 반도체 칩의 집적도가 올라가고 System-on-Chip(Soc)환경이 보편화되면서 Automatic Test Equipment(ATE)를 이용한 테스트 수행시 테스트 패턴의 크기 문제와 스캔체인에서의 전력 소모문제가 크게 부각되고 있다. 또한, 테스트 패턴 크기문제를 해결하기 위해 테스트 패턴을 압축하게 되면 테스트 패턴의 소모하는 전력량이 커지게 되어 저전력 테스트를 수행하는데 어려움이 있어 두 가지 문제를 해결할 수 없었다 본 논문에서는 이러한 문제점들을 동시에 해결하기 위해서 Run-length code를 기반으로 하여 저전력 테스트가 가능하면서 테스트 패턴의 크기도 줄일 수 있는 알고리즘을 제안하였다. 본 논문에서는 기존에 제시되었던 알고리즘과 비교ㆍ분석하는 실험을 통하여 이 알고리즘의 효율성을 보여주고 있다.

• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.