• ETRI Journal
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• 제25권5호
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.892-895
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• 2011

SoC(System-On-Chip)을 테스트 하는 동안 소모하는 전력소모는 SoC내의 IP 코어가 증가됨에 따라 매우 중요한 요소가 되었다. 본 논문에서는 Scan Latch Reordering과 Clock Gating 기법을 적용하여 scan-in 전력소모를 줄이는 알고리즘을 제안한다. Scan vector들의 해밍거리를 최소로 하는 새로운 Scan Latch Reordering을 적용하였으며 Gated scan 셀을 사용하여 저전력을 구현하였다. ISCAS 89 벤치마크 회로에 적용하여 실험한 결과 모든 회로에 대하여 향상된 전력소모를 보였다.

• 한국콘텐츠학회논문지
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• 제5권4호
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• pp.188-196
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• 2005

본 논문에서는 테스트 시간과 전력소모를 감축할 수 있는 새로운 테스트 데이터 압축 및 저전력 스캔 테스트 방법을 제안하였다. 제안된 방법은 수정된 스캔 셀 재배열과 하이브리드 적응적 부호화 방법을 사용하여 scan-in전력과 테스트 데이터 량을 줄였으며 하이브리드 테스트 데이터 압축방법은 Golomb Code와 런길이(run-length) 코드를 테스트 데이터내의 런(run) 길이에 따라서 적응적으로 적용하는 방법이다. 또한 scan-in 전력소모를 최소화하기 위해서 스캔 벡터내의 열 해밍거리를 이용하였다. ISCAS89 벤치마크 회로에 적용하여 실험한 결과, 모든 경우에 있어서 테스트 데이터 및 전력소모를 효율적으로 감소시켰으며 압축률은 17%-26%, 평균 전력소모는 8%-22%, 최고전력소모는 13%-60% 정도의 향상률을 보였다.

• 한국콘텐츠학회논문지
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• 제5권1호
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• pp.229-236
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• 2005

System-On-a-Chip(SOC)을 테스트하는 동안에 요구되는 테스트 시간과 전력소모는 SOC내의 IP 코어의 개수가 증가함에 따라서 매우 중요하게 되었다. 본 논문에서는 수정된 스캔 래치 재배열을 사용하여 scan-in 전력소모와 테스트 데이터의 양을 줄일 수 있는 새로운 알고리즘을 제안한다. 스캔 벡터 내의 해밍거리를 최소화하도록 스캔 래치 재배열을 적용하였으며 스캔 래치 재배열을 하는 동안에 스캔 벡터 내에 존재하는 don't care 입력을 할당하여 저전력 및 테스트 데이터 압축을 하였으며 ISCAS 89 벤치마크 외호에 적용하여 모든 경우에 있어서 테스트 데이터를 압축하고 저전력 스캔 테스팅을 구현하였다.

• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• ETRI Journal
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• 제30권3호
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• 대한전자공학회논문지SD
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• 제39권12호
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• pp.1045-1054
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• 2002

System-On-a-Chip(SOC)에 대하여 테스트 데이터 압축 및 저전력 스캔테스팅에 대한 새로운 알고리즘을 제안하였다. 스캔벡터내의 don't care 입력들을 저전력이 되도록 적절하게 값을 할당하였고 높은 압축율을 갖도록 적응적 인코딩을 적용하였다. 또한 스캔체인에 입력되는 동안 소모되는 scan-in 전력소모를 최소화하도록 스캔벡터의 입력 방향을 결정하였다. ISCAS 89 벤치마크 회로에 대하여 실험한 결과는 평균전력 소모는 약 12% 감소되었고 압축율은 약 60%가 향상됨을 보였다.