• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.434-438
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• 2000

In this paper the low cost sensorless control circuit for a PM synchronous motor without the mechanical rotor position sensors is presented. The sensorless control algorithm and position detection circuit for the sinusoidal current wave drive is more complex than that of the rectangular current wave drive. The proposed position sensing circuit is composed of an operational amplifier and several passive elements. The design procedures for getting the optimal parameters for the position sensing circuit are presented. The performance of the proposed algorithm is verified through the simulations and experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2014-2019
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• 2006

PDP driving circuit requires switching devices and capacitors to stand up high voltages over 160V. This is the main cause that the power consumption and the cost of a PDP driving circuit increase. Conventional PDP driving circuits consist of 3 voltage sources and 16 switching devices. In this paper, we propose a PDP driving circuit using 2 voltage sources and 12 switching devices that can be operated with a lower supply voltage than conventional driving circuit. The operation of the proposed driving circuit is verified by the computer simulation. Simulation results show that the output signal can drive PDP cell when the supply voltage is higher than 45V in the input frequency range 70kHz to 100kHz.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1951-1953
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• 2004

In this study, we propose a small high voltage power supply which use a half-bridge ZCS resonant and Cockroft-Walton on circuit, for ESP (Electrostatic Precipitator). This power supply transfers energy from ZCS resonant inverter to step-up transformer and the transformer secondary is applied to the Cockroft-Walton circuit for generating high voltage as discharging source of electrodes. It is highly efficient because its amount of switching losses are reduced by virtue of the current resonant half-bridge inverter, and also due to the small size, low parasitic capacitance in the transformer stage owing to the low number of winding turns of the step up transformer secondary combined with the Cockroft-Walton circuit. From these results, the best operational condition is obtained at the switching frequency of 9 kHz and the duty ratio of 50 % in this ESP.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.337-340
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• 2002

This paper describes a phase compensation technique for the low power consumption OTA. Power consumption of the low power OTA is lower than that of the conventional Wang's OTA. However. this circuit has an oscillation problem. The phase margin is -24deg. By using the phase compensation capacitor, the phase margin becomes 52deg. As a result, the low power consumption OTA circuit becomes to have an enough phase margin and to operate stably.

• ETRI Journal
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• v.35 no.2
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• pp.226-233
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• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1429-1437
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• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.