• 대한전기학회논문지:전력기술부문A
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• 제48권10호
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• 대한전자공학회논문지
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• 제24권4호
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.

• 한국전자통신학회논문지
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• 제11권1호
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• pp.29-36
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• 2016

최근 들어 양자 논리 회로의 저비용 실현 가능성을 가진 $NCV-{\mid}v_1$ >라이브러리라 불리는 새로운 종류의 양자 게이트가 주목을 받고 있다. $NCV-{\mid}v_1$ > MCT 게이트는 입력부에 타깃 입력을 제어하는 $CV-{\mid}v_1$ > 게이트와 정크 비트 제거를 위한 수반 게이트의 종속 AND 구조를 갖는다. 본 논문은 $NCV-{\mid}v_1$ >라이브러리에 대응하는 대칭적 쌍대 특성을 갖는 $NCV^{\dag}-{\mid}v_1$ >라이브러리라 불리는 새로운 게이트를 제안한다. 새로운 $NCV^{\dag}-{\mid}v_1$ >라이브러리는 특정 조건에서 OR 논리로 작동한다. $NCV-{\mid}v_1$ >라이브러리와 $NCV^{\dag}-{\mid}v_1$ >라이브러리를 함께 사용하면 MPMCT 게이트와 SOP 및 POS형 양자논리 회로의 저비용 실현이 가능하며, 순방향과 역방향 연산에 대한 상이한 연산 속성 때문에 듀얼 게이트 성질이 기대된다.

• 대한전자공학회논문지SD
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• 제40권10호
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• pp.52-62
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• 2003

본 논문에서는 3치 논리 게이트, 3치 D 플립플롭과 3치 4-디지트 병렬 입력/출력 레지스터를 제안하였다. 3치 논리 게이트는 n 채널 패스 트랜지스터와 뉴런 MOS(νMOS) 임계 인버터로 구성된다. 3치 논리 게이트들은 다양한 임계 전압을 갖는 다운 리터럴 회로를 사용하였고 전송함수를 바탕으로 설계되었다. 뉴런 MOS 트랜지스터는 다치 논리 구현에 가장 적합한 게이트이고 다양한 레벨의 입력 신호를 갖는다. 3치 D 플립 플롭과 3치 레지스터는 3치 데이터를 임시로 저장할 수 있는 저장 장치로 사용할 수 있다. 본 논문에서는 3.3V의 전원 전압을 사용하였고 0.35um 공정 파라미터를 이용하여 모의 실험을 통해 그 결과를 HSPICE로 검증하였다.

• 전기전자학회논문지
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• 제8권1호
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• pp.33-38
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• 2004

다치 논리 패스 게이트는 다치 논리를 구성하기 위한 중요한 소자이다. 본 논문에서는, 뉴런 $MOS({\nu}MOS)$ 임계 게이트를 갖는 2중 패스-트랜지스터 논리를 이용하여 4치 MIN(QMIN)/negated MIN(QNMIN) 게이트 그리고 4치 MAX(QMAX)/negated MAX(QNMAX) 게이트를 설계하였다. DPL은 입력 캐패시턴스의 증가 없이 게이트 속도를 향상 시켰다. 또한 대칭 배열과 2중 전송 특성을 갖는다. 임계 게이트는 ${\nu}MOS$ 다운 리터럴 회로(DLC)로 구성 된다. 제안된 게이트는 다양한 다치 임계 전압을 실현할 수 있다. 본 논문에서, 회로는 3V의 전원 전압을 사용하였고 0.35um N-Well 2-poly 4-metal CMOS 공정의 파라메터를 사용하였으며 모든 모의 실험은 HSPICE를 이용하였다.

• 대한임베디드공학회논문지
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• 제7권2호
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• pp.79-84
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• 2012

Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.

• Journal of the Optical Society of Korea
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• 제19권3호
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• pp.222-227
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• 2015

We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권10호
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• pp.510-514
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• 2004

In this paper, we analytically examine the voltage transfer function dependent on input conditions for an N-Input NAND Gate. The logic threshold voltage, defined as a voltage at which the input and the output voltage become equal, changes as the input condition changes for a static NAND Gate. The logic threshold voltage has the highest value when all the N-inputs undergo transitions and it has the lowest value when only the last input connected to the last NMOS to ground, makes a transition. This logic threshold voltage difference increases as the number of inputs increases. Therefore, in order to provide a near symmetric voltage transfer function, a multistage N-Input Gate consisting of 2-Input Logic Gates is desirable over a conventional N-Input Gate.

• 대한전자공학회논문지
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• 제14권6호
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• pp.10-15
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• 1977

This paper proposes a simple and systematic method for the generation of the fault detection test sets for the combinational logic networks. Based on tile path sensitizing concept, the test patterns for the primary input gates of the network are defined, and then it is shown that, arranging these predefined test patterns according to the path sensitizing characteristics of the given network sturctures, the minimal complete test sets for the fan-out free combinational networks can be found easily. It is also shown that, taking into account the fan-out paths sensitizing compatibility, the proposed method can be extended to the irredundant reconvergent fan-out networks.

• 한국광학회:학술대회논문집
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• 한국광학회 2001년도 제12회 정기총회 및 01년도 동계학술발표회
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• pp.150-151
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• 2001

광컴퓨터에 있어서 비선형 물질의 역할은 매우 중요하다. 그러한 비선형 물질들은 빛과 상호작용하고 빛의 성질을 변조시킨다. 광컴퓨터의 몇몇 구성 성분들은 그들이 작용하는데 있어서 중요한 비선형물질을 필요로 한다. 하지만 모든 광학적 장치들의 사용이 사실상 제한되는 것은 현재 이용할 수 있는 비선형 광물질이 비효과적이고 응답과 스위칭에 대해서 많은 에너지를 필요로 하기 때문이다. (중략)