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http://dx.doi.org/10.14372/IEMEK.2012.7.2.079

Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m)  

Kim, Kee-Won (우석대학교)
Lee, Won-Jin (단국대학교)
Kim, HyunSung (경일대학교 컴퓨터공학부)
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.7, no.2, 2012 , pp. 79-84 More about this Journal
Abstract
Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.
Keywords
Exponentiation; Modular multiplication; Finite field; Public-key cryptosystem;
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