• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.9
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• pp.745-752
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• 1990

This paper deals with the path sensitization algrithm from PI to PO center on the nodes of high testability mainstay when CUT is tested by pseudo exhaustive testing. In CUT, the node definition of high testability mainstay treats the testability values of the entire nodes with the population composed of the raw data, and after we examined the level of significance(1-a) region, we accomplished in the estimation of the confidence interval of the testability. Focusing on the defined nodes of high testability mainstay, we performed the singular cover and consistency operation to the forward and backward logic gates. Thus, we easily generated the pseudo exhausitve test patterns. As a result, (1-a) region has 0.1579 and the pseudo exhaustive test patterns are least generated and the rate of test pattern is 1.22%, compared with exhaustive testing. (1-a) region has 0.2368 and this results exhibits the optimal performance of the singular cover and consistency operation. Applying the generated pseudo exhaustive test patterns to the stuck-at faults existing on the inputs and internal nodes in CUT, we verified this performance on the output. Thus, it is confirmed that functional testing of the proposed path sensitization algorithm is very useful.

• Transactions on Electrical and Electronic Materials
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• v.6 no.4
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• pp.154-158
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• 2005

Organic molecules have many properties that make them attractive for electronic applications. We have been examining the progress of memory cell by using molecular-scale switch to give an example of the application using both nano scale components and Si-technology. In this study, molecular electronic devices were fabricated with amino style derivatives as redox-active component. This molecule is amphiphilic to allow monolayer formation by the Langmuir-Blodgett (LB) method and then this LB monolayer is inserted between two metal electrodes. According to the current-voltage (I-V) characteristics, it was found that the devices show remarkable hysteresis behavior and can be used as memory devices at ambient conditions, when aluminum oxide layer was existed on bottom electrode. The diode-like characteristics were measured only, when Pt layer was existed as bottom electrode. It was also found that this metal layer interacts with organic molecules and acts as a protecting layer, when thin Ti layer was inserted between the organic molecular layer and Al top electrode. These electrical properties of the devices may be applicable to active components for the memory and/or logic gates in the future.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.269-277
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• 1996

This paper has been presented a design of a POCSAG decoder in RT-level VHDL and implemented in a FPGA chip, and tested. In a single clock of 76.8KHz, the decoder receives all the data of the rate of 512/1200/2400bps and has maximum 2-own frames for service enhancement. To improve decoder performance, the decoder uses a preamble detection cosidering 9% frequency tolerance, a SCW detction and a ICW detection at each 4 bit. The decoder also corrects a address data and a message data up to 2 bits and proposes the PF (preamble frequency) error for saving battery. The decoder increases a battery life owing to turn off RF circuits when the preamble signal is detected with nises. The chip has been designed in RT-level VHdL, synthesized into logic gates using power view$^{TM}$ of viewlogic software. The chip has been implemented in an ALTERA EPF81188GC232-3 FPGA chip with 98% usability, and fully tested in shield room and field room. The chip has been proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system using PDI 2400 through the real field test. The receiving performance is improved by 20% of aaverage, compared with other existing systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.57-66
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• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.