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A Parallel Hardware Architecture for H.264/AVC Deblocking Filter  

Jeong, Yong-Jin (Dept. of Electronics and Communication Engineering, Kwangwon University)
Kim, Hyun-Jip (Dept. of Electronics and Communication Engineering, Kwangwon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.10, 2006 , pp. 45-53 More about this Journal
Abstract
In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.
Keywords
H.264/AVC; deblocking filter;
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