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Efficient DSP Architecture for Viterbi Algorithm  

Park Weon heum (삼성전자 통신연구소)
Sunwoo Myung hoon (아주대학교 정보통신대학 전자공학부)
Oh Seong keun (아주대학교 정보통신대학 전자공학부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.3A, 2005 , pp. 217-225 More about this Journal
Abstract
This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.
Keywords
DSP;
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  • Reference
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