• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.267-273
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• 2003

The plasma display panel with the electrode structure of new discharge AND gate and its driving scheme were proposed and the driving system for experiment was developed. And operation of these discharge AND gate was verified by the experiment of PDP addressing with floating electrode. This discharge AND gate operated by the operation speed of 8$mutextrm{s}$ and the operation margin of 100V. The address operation margin of 10V also obtained. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because proposed method uses the DC discharge the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the input discharge and the output discharge of discharge gate are separate, the display discharge can be prevented from passing discharge gates. Therefore, it is possible to apply to the large screen plasma display panel. And the decrease of contrast ratio does not occur because the scanning discharge does not influence the picture quality.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1113-1116
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• 1998

This paper presents an efficient hardware architecture of demodulating fingers to demodulate the multi-path propagating signals in MC-CDMA Mobile System. We design a new architecture of demodulating fingers which share the single arithmetic unit to reduce the hardware complexity. This arithmetic unit performs MAC(Multiplication and Accumulation) operations of all demodulating fingers. The proposed architecture is suitable for Is-95 based CDMA PCS system. Three demodulating fingers for MC-CDMA which demodulate 7 channels contain about 42K logic gates. Our proposed system is shown to be very useful for Multi-Code CDMA system in which several channels are demodulated simultaneously.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.185-192
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• 2010

This paper presents a hardware-efficient auto-correlation scheme for the synchronization of MIMO-OFDM based wireless local area network (WLAN) systems, such as IEEE 802.11n. Carrier frequency offset (CFO) estimation for the frequency synchronization requires high complexity auto-correlation operations of many training symbols. In order to reduce the hardware complexity of the MIMO-OFDM synchronization, we propose an efficient correlation scheme based on time-multiplexing technique and the use of reduced samples while preserving the performance. Compared to a conventional architecture, the proposed architecture requires only 27% logic gates and 22% power consumption with acceptable BER performance loss.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.04a
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• pp.387-394
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• 1995

With respect to the effectiveness of types of knowledge on human diagnostic performance, the results of several experiments claimed that training with diagnostic rules (procedural knowledge) is more effective than training that provides theoretical knowledge (principle knowledge). However, we usually have the idea that understanding the principles of system dynamics is necessary for diagnosis in some situations. In this study, we pointed out some problems in the previous experiments that force to reinterpret their experimental conclusions. Accordingly, we conducted an experiment to reinvestigate the value of theoretical knowledge in two problem situations. A simulator system, which is named DLD, that is to diagnose an electronic device was created for this purpose. It is a context-free digital logic circuit which includes forty-one gates of three basic types. Our experiment investigated the marginal effects of theoretical knowledge over common diagnostic rules. The experimental results showed that the effectiveness of the instruction in theoretical knowledge is dependent on the complexity of diagnostic situations. This adds up an experimental evidence against the presumed ineffectiveness of theoretical knowledge and forward reasoning in fault diagnosis. Furthermore, the result suggests the source of the use of theoretical knowledge.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1481-1484
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• 1987

The ALU of CMOS microcomputer have been designed with the 3um design rule for CMOS polysilicon gate and Its cells were layed out. The operation of circuits were simulated with EDAS_P. The widths and lengths of gates In the circuit were determined using SPlCE. The carry delay of the ALU was Improved by Manchester carry method. The results of logic and circuit simulation were in good agreement with expected circuit characteristics.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1560-1563
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• 1987

This paper is concerned with time delay modeling of ED MOS gates which takes into account the slope of input waveform as well as the load condition. Defining the delay time as the time required to charge/discharge the load to the physical reference level, the rise/fall delay times arc derived in an explicit formula in terms of the sum of optimally weighted current unbalances at two end points of voltage transition. The proposed model is computationally effective and the error is typically within 10% of the SPICE results.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.