• Journal of the Korea Convergence Society
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• v.12 no.10
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• pp.19-25
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• 2021

This study contains the results obtained after two and a half years of developing a knitting customization website using a knitting machine. Recently in the fashion world, various services using customization are being provided, and devices that users can design directly using knitting machines are being developed. However the existing website for knitting machine does not provide a certain usability or layout, so it is difficult for users to use open source and custom design. Therefore, this study was conducted for the purpose of developing a website that provides ease of use to users who will use the knitting customizing service using a knitting machine. As a research method, the first usability evaluation was conducted by synthesizing the studies conducted for the knit customization website development work. As a result of the study, found the problems of the initial custom screen and the initial output screen were found, and convenience, intuition, and readability were improved. Secondary usability evaluation was conducted on the modified website and it was confirmed that the problem was corrected. Through the website finally derived from this study, it is expected that the new platform in the domestic knit market will be popularized and the usability of the custom website will be improved.

• Journal of the Korea Convergence Society
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• v.12 no.8
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• pp.23-30
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• 2021

Various customizing services are also being introduced in the fashion industry in line with the diversification of consumer tastes and the demand for small production of multiple varieties. However, barriers to entry are high for consumers who are not customized, and various functions are rather complicated. This study selected the three platforms that provide the most similar services to Marple, the No. 1 fashion platform sales, as comparative models and used them as a basic study for web-based fashion customization platform design through case analysis. As a research method, theoretical examinations were conducted through literature surveys, followed by web analysis based on layout, menu, color, icon, and interaction. The study found that the placement of options, the composition of menu windows, the number of point colors, and the use of icons without functions of metaphores hindered the use of customizing platforms. This work proposes a solution, and aims to contribute to increasing the usability of future customizing web by comprehensively analyzing the visual shaping elements of web platform design.

• Journal of the Korea Society for Simulation
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• v.18 no.3
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• pp.23-34
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• 2009

In the railroad rolling stock depot, long-term maintenance tasks is done regularly every two or four year basis to maintain the functionality of equipments and rolling stock body or for the repair operation of the heavily damaged rolling stocks by fatal accidents. This paper addresses the computer simulation model building for the rolling stock maintenance shop for the CDC(Commuter Diesel Car) and Generator Car planned to be constructed at Daejon Rolling Stock Depot, which will be moved from Yongsan Rolling Stock Depot. We evaluated the processing capacity of two layout design alternatives based on the maintenance process chart through the developed simulation models. The performance measures are the number of processed cars per year, the cycle time, shop utilization, work in process and the average number waiting car for input. The simulation result shows that one design alternative outperforms another design alternative in every aspect and superior design alternative can process total 340 number of trains per year 15% more than the proposed target within the current average cycle time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.