• 한국전기전자재료학회논문지
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• 제31권3호
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.245-251
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• 2013

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.381-382
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• 2018

무접합 나노선 터널 전계 효과 트렌지스터(junctionless nanowire tunnel field-effect transistor; JLNW-TFET)에서 소스(p+), 채널(i), 드레인(n) 물질으로 실리콘 및 게르마늄을 사용하여 이 구조에 대한 문턱전압 이하 기울기(subthreshold swings; SS)와 구동전류를 관찰했다. 소스-채널을 게르마늄-실리콘일 때 실리콘-실리콘, 실리콘-게르마늄, 게르마늄-게르마늄 구조보다 구동전류가 최대 1000배 증가하였고, 실리콘-실리콘 구조가 다른 구조에 비해 최소 SS가 최대 5배 이상 감소하였다.

• 한국전기전자재료학회논문지
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• 제34권2호
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• pp.142-147
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• 2021

We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.

• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.129-135
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• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.266-268
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• 2013

In this paper, we study the channel doping concentration characteristics of junctionless nanowire transistors (JLT) using Edison nanowire FET device simulation. JLT has no junctions by very simple fabrication process. And this device has less variability and better electrical properties than classical inversion-mode transistors with PN junctions at the source and drain. In this simulation we use tri-gate structure. Source and drain doping concentration is $10^{20}atoms/cm^3$. The simulation results show that I-V characteristics of JLT change due to the variation of channel doping concentration.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.508-517
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• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.210.1-210.1
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• 2015

최근 산화물 반도체에 대한 연구가 활발하게 이루어지고 있다. 비정질 산화물 반도체인 In-Ga-Zn-O (IGZO)는 기존의 비정질 실리콘에 비해 공정 단가가 낮으며 넓은 밴드 갭으로 인한 투명성을 가지고 있고, 저온 공정이 가능하여 다양한 기판에 적용이 가능하다. 반도체의 공정 과정에서 열처리는 소자의 특성 개선을 위해 필요하다. 일반적인 열처리 방법으로 furnace 열처리 방식이 주로 이용된다. 그러나 furnace 열처리는 시간이 오래 걸리며 일반적으로 고온에서 이루어지기 때문에 최근 연구되고 있는 유리나 플라스틱, 종이 기판을 이용한 소자의 경우 기판이 손상을 받는 단점이 있다. 이러한 단점들을 극복하기 위하여 저온 공정인 마이크로웨이브를 이용한 열처리 방식이 제안되었다. 마이크로웨이브 열처리 기술은 소자에 에너지를 직접적으로 전달하기 때문에 기존의 다른 열처리 방식들과 비교하여 에너지 전달 효율이 높다. 또한 짧은 공정 시간으로 공정 단가를 절감하고 대량생산이 가능한 장점을 가지고 있으며, 저온의 열처리로 기판의 손상이 없기 때문에 기판의 종류에 국한되지 않은 공정이 가능할 수 있을 것으로 기대된다. 따라서 본 연구에서는 마이크로웨이브 열처리가 소자의 전기적 특성 개선에 미치는 영향을 확인하였다. 제작된 IGZO 박막트렌지스터는 p-type bulk silicon 위에 thermal SiO2 산화막이 100 nm 형성된 기판을 사용하였다. RCA 클리닝을 진행한 후 RF sputter를 사용하여 In-Ga-Zn-O (1:1:1)을 70 nm 증착하였다. 이후에 Photo-lithography 공정을 통하여 active 영역을 형성하였고, 전기적 특성 평가가 용이한 junctionless 트랜지스터 구조로 제작하였다. 후속 열처리 방식으로 마이크로웨이브 열처리를 1000 W에서 2분간 실시하였다. 그리고 기존 열처리 방식과의 비교를 위해 furnace를 이용하여 N2 가스 분위기에서 $600^{\circ}C$의 온도로 30분 동안 열처리를 실시하였다. 그 결과, 마이크로웨이브 열처리를 한 소자의 경우 기존의 furnace 열처리 소자와 비교하여 우수한 전기적 특성을 나타내는 것을 확인하였다. 따라서, 마이크로웨이브를 이용한 열처리 공정은 향후 저온 공정을 요구하는 소자 공정에 활용될 수 있을 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• 전기전자학회논문지
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• 제24권1호
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• pp.194-199
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• 2020

본 논문에서는 비대칭 무접합 이중게이트 MOSFET에 대한 문턱전압이동을 상단과 하단 게이트 산화막 두께에 따라 분석하였다. 비대칭 구조에서는 상단과 하단 게이트 산화막 두께를 달리 제작할 수 있으므로 문턱전압이동을 일정하게 유지하면서 상단 게이트에서 발생할 수 있는 누설전류를 감소시키기 위하여 상단과 하단 산화막 두께를 조정할 수 있다. 이를 위하여 해석학적 문턱전압 모델을 제시하였으며 이 모델은 2차원 시뮬레이션 값과 잘 일치하였다. 결과적으로 일정한 문턱전압이동을 유지하면서 하단 게이트 산화막 두께를 감소시키면 상단 게이트 산화막 두께를 증가시킬 수 있어 상단 게이트에서 발생할 수 있는 누설전류를 감소시킬 수 있을 것이다. 특히 하단 게이트 산화막 두께가 증가하여도 문턱전압이동에는 큰 영향을 미치지 않는다는 것을 관찰하였다.