Analyze the channel doping concentration characteristics of junctionless nanowire transistors by using Edison simulation

In this paper, we study the channel doping concentration characteristics of junctionless nanowire transistors (JLT) using Edison nanowire FET device simulation. JLT has no junctions by very simple fabrication process. And this device has less variability and better electrical properties than classical inversion-mode transistors with PN junctions at the source and drain. In this simulation we use tri-gate structure. Source and drain doping concentration is $10^{20}atoms/cm^3$. The simulation results show that I-V characteristics of JLT change due to the variation of channel doping concentration.