• 제목/요약/키워드: junction structure

검색결과 488건 처리시간 0.025초

Large Tunneling Magnetoresistance of a Ramp-type Junction with a SrTiO3 Tunneling Barrier

  • Lee, Sang-Suk;Yoon, Moon-Sung;Hwang, Do-Guwn;Rhie, Kung-Won
    • Journal of Magnetics
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    • 제8권2호
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    • pp.89-92
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    • 2003
  • The tunneling magnetoresistance (TMR) of a ramp-edge type junction with SrTiO$_3$barrier layer has been stud-ied. The samples with a structure of glass/NiO(600${\AA}$)/Co(100${\AA}$)/SrTiO$_3$(400 ${\AA}$)/SrTiO$_3$(20-100${\AA}$)/NiFe(100${\AA}$) were prepared by the sputtering and etched by the electron cyclotron (ECR) argon ion milling. Nonlinear I-V characteristics were obtained from a ramp-type tunneling junctions, having the dominant difference between two different external magnetic fields (${\pm}$100 Oe) perpendicular to the junction edge line. In the SrTiO$_3$ barrier thickness of 40${\AA}$, the TMR was 52.7% at a bias voltage of -50 mV The bias voltage dependence of resistance and TMR in a ramp-type tunneling junction was similar with those of the layered TMR junction.

공정조건에 따른 함몰된 다결정실리콘/실리콘($n^{+}$) - 실리콘(p) 접합의 특성 (Properties of Recessed Polysilicon/Silicon($n^{+}$) - Silicon(P) Junction with Process Condition)

  • 이종호;최우성;박춘배;이종덕
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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    • pp.152-153
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    • 1994
  • A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

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간극결합채널의 개폐기전 (Mechanism for Gating of Gap Junction Channel.)

  • 오승훈
    • 생명과학회지
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    • 제14권5호
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    • pp.882-890
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    • 2004
  • 간극결합(gap junction)은 이웃하는 두 세포사이에 형성된 막 구조물로 이를 통하여 각종 이온들과 여러 가지 분자들이 통과한다. 일반적으로 알려진 세포의 이온채널(예를 들어 $Na^{+}$ 이온채널과$K^+$이온채널)과 구별하여 두 세포사이에 형성된 간극결합을 세포간 채널(intercellular channel)이라고도 부른다. 간극결합채널(gap junction channel)은 단순히 수동적으로 열려있는 통로가 아니라 여러 가지 자극 즉 pH, 칼슘이온(calcium ion), 전압(voltage), 그리고 화학적인 변형(주로 인산화, phosphorylation)에 의해서 개폐(gating, opening and closing)가 조절되는 이온채널이다. 그 가운데서도 전압에 의한 간극결합채널 개폐 변화가 가장 많이 연구되었다. 세포안과 바깥에 형성된 전압차이(membrane potential, $V_m$) 보다는 주로 두 세포 사이에 형성된 전압차이(transjunctional voltage, $V_j$)에 의해서 간극결합채널은 민감하게 반응한다. 본 총설에서는 간극결합채널의 일반적인 특성을 정리해보고 전압-의존적인(voltage-dependent) 채널개폐에 관한 기전을 논의하고자 한다.

Super Junction IGBT 필러 내부 Trench SiO2성장에 따른 전기적 특성에 관한 연구 (A Study on the Electrical Characteristics according to Growth of Trench SiO2 Inside Super Junction IGBT Pillar)

  • 이건희;안병섭;강이구
    • 전기전자학회논문지
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    • 제25권2호
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    • pp.344-349
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    • 2021
  • Super Junction구조는 항복전압과 온-상태 전압강하의 트레이드-오프 특성을 개선하고자 제안된 구조이다. 본 논문은 Super Junction IGBT P-Pillar 내부 영역에 Trench SiO2를 성장시킨 구조를 제안한다. Super Junction구조에 인가되는 전계를 3D로 관찰 시 P-Pillar 내부에 전계가 인가되지 않는 영역을 확인하였다. Pillar영역의 부분저항은 각 Pillar의 크기와 항복전압에 의해 변동되는데 전계가 인가되지 않는 P-Pillar 내부 영역을 Trench 한 후 SiO2를 성장시켜 P-Pillar의 크기를 감소시킨다. 4.5kV의 동일한 항복전압을 가질 때 온-상태 전압강하 특성이 Field Stop IGBT 대비 약 58%, 기존의 Super Junction IGBT 대비 19% 향상되는 것을 확인하였다.

Thin Film Amorphous/Bulk Crystalline Silicon Tandem Solar Cells with Doped nc-Si:H Tunneling Junction Layers

  • 이선화;이준신;정채환
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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    • pp.257.2-257.2
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    • 2015
  • In this paper, we report on the 10.33% efficient thin film/bulk tandem solar cells with the top cell made of amorphous silicon thin film and p-type bulk crystalline silicon bottom cell. The tunneling junction layers were used the doped nanocrystalline Si layers. It has to allow an ohmic and low resistive connection. For player and n-layer, crystalline volume fraction is ~86%, ~88% and dark conductivity is $3.28{\times}10-2S/cm$, $3.03{\times}10-1S/cm$, respectively. Optimization of the tunneling junction results in fill factor of 66.16 % and open circuit voltage of 1.39 V. The open circuit voltage was closed to the sum of those of the sub-cells. This tandem structure could enable the effective development of a new concept of high-efficiency and low cost cells.

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Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate

  • Ali, Asif;Seo, Dongsun;Cho, Il Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권1호
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    • pp.156-161
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    • 2017
  • This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

Fabrication of Vertical Organic Junction Transistor by Direct Printing Method

  • Shin, Gunchul;Kim, Gyu-Tae;Ha, Jeong Sook
    • Bulletin of the Korean Chemical Society
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    • 제35권3호
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    • pp.731-736
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    • 2014
  • An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.

경계항복 억제를 위한 평판형 InP/InGaAs 애벌랜치 포토다이오드의 곡률 효과 분석 (Investigation of Curvature Effect on Planar InP/InGaAs Avalanche Photodiodes for Edge Breakdown Suppression)

  • 이봉용;정지훈;윤일구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.206-209
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    • 2002
  • With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

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3.3kV급 저저항 4H-SiC Semi-SJ MOSFET (3.3kV Low Resistance 4H-SiC Semi-SJ MOSFET)

  • 천진희;김광수
    • 전기전자학회논문지
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    • 제23권3호
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    • pp.832-838
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    • 2019
  • 본 논문에서는 차세대 전력 반도체 소자인 4H-SiC MOSFET에 대해 연구하였다. 특히 3300V급에서 기존의 DMOSFET 구조보다 개선된 전기적 특성을 갖는 Semi-SuperJunction MOSFET 구조를 제안하였으며, TCAD 시뮬레이션을 통해 기존의 MOSFET과 전기적 특성을 비교 분석하였다. Semi-SJ MOSFET 구조는 부분적으로 SJ를 도입한 구조로, 2차원의 공핍 효과를 통해 전계 분포가 개선되며, 항복 전압이 증가한다. 항복 전압의 개선을 통해 얻은 이득으로, 높은 농도의 도핑이 가능하기 때문에 온 저항을 개선시킬 수 있다. 제안한 Semi-SJ MOSFET 구조는 DMOSFET보다 항복 전압이 8% 감소하지만, 온 저항이 80% 감소한다. 또한 DMOSFET 구조를 개선한 Current Spreading Layer(CSL)구조에 비해서도 온 저항이 44% 감소한다.

Shallow S/D Junction에 적용 가능한 NiSi를 형성하기 위한 Ni-Pd 합금의 특성 연구 (The Study of Ni-Pd Alloy Characteristics to Form a NiSi for Shallow S/D Junction)

  • 이원재;오순영;아그츠바야르투야;윤장근;김용진;장잉잉;종준;김도우;차한섭;허상범;왕진석;이희덕
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.603-606
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    • 2005
  • In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

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