• Title/Summary/Keyword: junction leakage current

Search Result 93, Processing Time 0.041 seconds

A Study on High Performance Lateral Super Barrier Rectifier for Integration in BCD (Bipolar CMOS DMOS) Platform (BCD Platform과의 집적화에 적합한 고성능 Lateral Super Barrier Rectifier의 연구)

  • Kim, Duck-Soo;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.28 no.6
    • /
    • pp.371-374
    • /
    • 2015
  • This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.

A Study on the Diffusion Barrier Properties of Pt/Ti and Ni/Ti for Cu Metallization (구리 확산에 대한 Pt/Ti 및 Ni/Ti 확산 방지막 특성에 관한 연구)

  • 장성근
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.16 no.2
    • /
    • pp.97-101
    • /
    • 2003
  • New Pt/Ti and hi/Ti double-metal structures have been investigated for the application of a diffusion barrier between Cu and Si in deep submicron integrated circuits. Pt/Ti and Ni/Ti were deposited using E-beam evaporator at room temperature. The performance of Pt/Ti and Ni/Ti structures as diffusion barrier against Cu diffusion was examined by charge pumping method, gate leakage current, junction leakage current, and SIMS(secondary ion mass spectroscopy). These evaluation indicated that Pt/Ti(200${\AA}$/100${\AA}$) film is a good barrier against Cu diffusion up to 450$^{\circ}C$.

Electric properties Analysis and fabrication of ZnO:As/ZnO:Al homo-junction LED (ZnO:As/ZnO:Al homo-junction LED의 제조와 전기적 특성 분석)

  • Kim, Kyeong-Min;So, Soon-Jin;Park, Choon-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2007.06a
    • /
    • pp.55-56
    • /
    • 2007
  • The p-type ZnO thin film, fabricated by means of the ampoule-tube method, was used to make the ZnO p-n junction, and its characteristics was analyzed. The ampoule-tube method was used to make the p-type ZnO based on the As diffusion, and the hall measurement was used to confirm that the p-type is formed. the current-voltage characteristics of the ZnO p-n junction were measured to confirm the rectification characteristics of a typical p-n junction and the low leakage voltage characteristics. Using the ampoule-tube to fabricate the p-type ZnO will provide a very useful technology for producing the UV ZnO LED and ZnO-based devices.

  • PDF

Analysis on the V-I Curve of ZnO:As/ZnO:Al homo-junction LED (ZnO:As/ZnO:Al homo-junction LED의 V-I 특성 분석)

  • Oh, Sang-Hyun;Jeong, Yun-Hwan;Liu, Yan-Yan;Park, Choon-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2007.11a
    • /
    • pp.410-411
    • /
    • 2007
  • To investigate the ZnO LED which are interested in the next generation of short wavelength LEDs and Lasers, the ZnO thin films were deposited by RF magnetron sputtering system. The p-type ZnO thin film, fabricated by means of the ampoule-tube method, was used to make the ZnO p-n junction, and its characteristics was analyzed. The ampoule-tube method was used to make the p-type ZnO based on the As diffusion, and the hall measurement was used to confirm that the p-type is formed. the current-voltage characteristics of the ZnO p-n junction were measured to confirm the rectification characteristics of a typical p-n junction and the low leakage voltage characteristics. Analysis of ZnO LED V-I curve will provide a very useful technology for producing the UV ZnO LED and ZnO-based devices.

  • PDF

Formation of the Shallow $p^+$ -n Junction by As-Preamorphization Method and Characterization (비소 비정질화 방법에 의한 얕은 $p^+$-n 접합의 형성과 특성분석)

  • Sang Jik Kwon
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.30A no.11
    • /
    • pp.113-121
    • /
    • 1993
  • In the formation of the shallow p$^{+}$-n junction, the preamorphization method by As$^{+}$ ions was applied in order to avoid the boron channeling effect which is occured during the B$^{+}$ implantation especially with low energy. By As$^{+}$ pre-implant with 60KeV energy and 2*10$^{14}$ cm$^{-2}$ dose, the channelinf of B$^{+}$ ions implanted with 10keV/1.5*10$^{14}$ cm$^{-2}$ can be avoded completely. After the RTA of 1050.deg. C and 10sec, the junction depth was 0.14.mu.m, the leakage current was 20nA/cm$^{2}$(at-5V bias) and the sheet resistance was 107.OMEGA./ㅁ. And the preamorphized Si layer was changed into the perfect crystal si after the RTA.r the RTA.

  • PDF

Design and Fabrication of Buried Channel Polycrystalline Silicon Thin Film Transistor (Buried Channel 다결정 실리콘 박막 트랜지스터의 설계 및 제작)

  • 박철민;강지훈;유준석;한민구
    • Journal of the Korean Institute of Telematics and Electronics D
    • /
    • v.35D no.12
    • /
    • pp.53-58
    • /
    • 1998
  • A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

  • PDF

A Modified Single-Phase Transformerless Z-Source Photovoltaic Grid-Connected Inverter

  • Liu, Hongpeng;Liu, Guihua;Ran, Yan;Wang, Gaolin;Wang, Wei;Xu, Dianguo
    • Journal of Power Electronics
    • /
    • v.15 no.5
    • /
    • pp.1217-1226
    • /
    • 2015
  • In a grid-connected photovoltaic (PV) system, the traditional Z-source inverter uses a low frequency transformer to ensure galvanic isolation between the grid and the PV system. In order to combine the advantages of both Z-source inverters and transformerless PV inverters, this paper presents a modified single-phase transformerless Z-source PV grid-connected inverter and a corresponding PWM strategy to eliminate the ground leakage current. By utilizing two reversed-biased diodes, the path for the leakage current is blocked during the shoot-through state. Meanwhile, by turning off an additional switch, the PV array is decoupled from the grid during the freewheeling state. In this paper, the operation principle, PWM strategy and common-mode (CM) characteristic of the modified transformerless Z-source inverter are illustrated. Furthermore, the influence of the junction capacitances of the power switches is analyzed in detail. The total losses of the main electrical components are evaluated and compared. Finally, a theoretical analysis is presented and corroborated by experimental results from a 1-kW laboratory prototype.

The Technology of Sloped Wall SWAMI for VLSI and Analysis of Leakage Current (고집적 회로를 위한 경사면 SWAMI 기술과 누설전류 분석)

  • 이용재
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.15 no.3
    • /
    • pp.252-259
    • /
    • 1990
  • This paper present new scheme for a Side Wall Masked Isolation(SWAMI) technology which take all the advatages provided by conventional LOCOS process. A new SWAMI process incorporates a sloped sidewall by reactive ion etch and a layer of thin nitride around the side walls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. As a fabricate results, a defect-free fully recessed zero bird's beak local oxidation process can be realized by the sloped wall anisotropic oxide isolation. No additional masking step is required. The leakage current of PN diodes of this process were reduced than PN diode of conventional LOCOS process. On the other hand, the edge junction part was larger than the flat juction part in the density of leakage current.

  • PDF

Study on the Blocking Voltage and Leakage Current Characteristic Degradation of the Thyristor due to the Surface Charge in Passivation Material (표면 전하에 의한 Thyristor 소자의 차단전압 및 누설전류특성 연구)

  • Kim Hyoung-Woo;Seo Kil-Soo;Bahng Wook;Kim Ki-Hyun;Kim Nam-Kyun
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.55 no.1
    • /
    • pp.34-39
    • /
    • 2006
  • In high-voltage devices such as thyristor, beveling is mostly used junction termination method to reduce the surface electric field far below the bulk electric field and to expand the depletion region thus that breakdown occurs in the bulk of the device rather than at the surface. However, coating material used to protect the surface of the device contain so many charges which affect the electrical characteristics of the device. And device reliability is also affected by this charge. Therefore, it is needed to analyze the effect of surface charge on electrical characteristics of the device. In this paper, we analyzed the breakdown voltage and leakage current characteristics of the thyristor as a function of the amount of surface charge density. Two dimensional process simulator ATHENA and two-dimensional device simulator ATLAS is used to analyze the surface charge effects.

Properties of Recessed Polysilicon/Silicon($n^{+}$) - Silicon(P) Junction with Process Condition (공정조건에 따른 함몰된 다결정실리콘/실리콘($n^{+}$) - 실리콘(p) 접합의 특성)

  • 이종호;최우성;박춘배;이종덕
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 1994.05a
    • /
    • pp.152-153
    • /
    • 1994
  • A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

  • PDF