• 제목/요약/키워드: inverter topology

검색결과 375건 처리시간 0.027초

A New Single Phase Multilevel Inverter Topology with Two-step Voltage Boosting Capability

  • Roy, Tapas;Sadhu, Pradip Kumar;Dasgupta, Abhijit
    • Journal of Power Electronics
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    • 제17권5호
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    • pp.1173-1185
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    • 2017
  • In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.

Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor

  • Angamuthu, Rathinam;Thangavelu, Karthikeyan;Kannan, Ramani
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권1호
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    • pp.58-69
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    • 2016
  • This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.

Three-Phase Four-Wire Inverter Topology with Neutral Point Voltage Stable Module for Unbalanced Load Inhibition

  • Cai, Chunwei;An, Pufeng;Guo, Yuxing;Meng, Fangang
    • Journal of Power Electronics
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    • 제18권5호
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    • pp.1315-1324
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    • 2018
  • A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

Single-Phase Multilevel PWM Inverter Based on H-bridge and its Harmonics Analysis

  • Choi, Woo-Seok;Nam, Hae-Kon;Park, Sung-Jun
    • Journal of Power Electronics
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    • 제15권5호
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    • pp.1227-1234
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    • 2015
  • The efficient electric power demand management in electric power supply industry is currently being changed by distributed generation. Meanwhile, small-scale distributed generation systems using renewable energy are being constructed worldwide. Several small-scale renewable distributed generation systems, which can supply electricity to the grid at peak load of the grid as per policy such as demand response programs, could help in the stability of the electric power demand management. In this case, the power quality of the small-scale renewable distributed generation system is more significant. Low prices of power semiconductors and multilevel inverters with high power quality have been recently investigated. However, the conventional multilevel inverter topology is unsuitable for the small-scale renewable distributed generation system, because the number of devices of such topology increases with increasing output voltage level. In this paper, a single-phase multilevel inverter based on H-bridge, with DC_Link divided by bi-directional switches, is proposed. The proposed topology has almost half the number of devices of the conventional multilevel inverter topology when these inverters have the same output voltage level. Double Fourier series solution is mainly used when comparing PWM output harmonic components of various inverter topologies. Harmonic components of the proposed multilevel inverter, which have been analyzed by double Fourier series, are compared with those of the conventional multilevel inverter. An inverter prototype is then developed to verify the validity of the theoretical analysis.

스위치 저감형 Z-Source Inverter PWM 제어 (PWM Control of Reduced Switch Z-Source Inverter)

  • 김성환;박태식
    • 전기전자학회논문지
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    • 제23권1호
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    • pp.53-57
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    • 2019
  • 본 논문에서는 스위칭 소자를 줄이기 위한 새로운 Z-소스 인버터의 구조와 PWM 펄스 제어 방법에 대하여 제안하였다. 개선된 Z-소스 인버터는 Z-네트워크가 DC전압과 인버터 사이가 아닌 인버터 뒷단과 접지 사이에 연결되며, 이러한 개선된 Z-소스 인버터는 커패시터 돌입 전류 제한 기능과 커패시터 전압 스트레스가 작은 장점을 가지고 있다. 개선된 Z-소스 인버터에서 스위치를 6개에서 4개로 줄이는 새로운 형태의 스위치 저감형 Z-소스 인버터의 Topology를 제안하고, 제안된 Topology에 적합한 PWM 제어 방법을 개발하였다. 제안된 방법은 PSIM 시뮬레이션을 통해 특성과 성능을 확인하였다.

Transformer-Less Single-Phase Four-Level Inverter for PV System Applications

  • Yousofi-Darmian, Saeed;Barakati, Seyed Masoud
    • Journal of Power Electronics
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    • 제14권6호
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    • pp.1233-1242
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    • 2014
  • A new inverter topology for single-phase photovoltaic (PV) systems is proposed in this study. The proposed inverter offers a four-level voltage in its output terminals. This feature results in easier filtering in comparison with other conventional two-level or three-level inverters. In addition, the proposed four-level inverter (PFLI) has a transformer-less topology, which decreases the size, weight, and cost of the entire system and increases the overall efficiency of the system. Although the inverter is transformer-less, it produces a negligible leakage ground current (LGC), which makes this inverter suitable for PV grid-connected applications. The performance of the proposed inverter is compared with that of a four-level neutral point clamped inverter (FLNPCI). Theoretical analysis and computer simulations verify that the PFLI topology is superior to FLNPCI in terms of efficiency and suitability for use in PV transformer-less systems.

A New Single-Phase Asymmetrical Cascaded Multilevel DC-Link Inverter

  • Ahmed, Mahrous;Hendawi, Essam
    • Journal of Power Electronics
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    • 제16권4호
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    • pp.1504-1512
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    • 2016
  • This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

A Dual Buck Three-Level PV Grid-Connected Inverter

  • Ji, Baojian;Hong, Feng;Wang, Jianhua;Huang, Shengming
    • Journal of Power Electronics
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    • 제15권4호
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    • pp.910-919
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    • 2015
  • The use of a PV grid-connected inverter with non-isolated topology and without a transformer is good for improving conversion efficiency; however, this inverter has become increasingly complicated for eliminating leakage current. To simplify the complicated architecture of traditional three-level dual buck inverters, a new dual Buck three-level PV grid-connected inverter topology is proposed. In the proposed topology, the voltage on the grounding stray capacitor is clamped by large input capacitors and is equal to half of the bus voltage; thus, leakage current can be eliminated. Unlike in the traditional topology, the current in the proposed topology passes through few elements and does not flow through the body diodes of MOSFET switches, resulting in increased efficiency. Additionally, a multi-loop control method that includes voltage-balancing control is proposed and analyzed. Both simulation and experimental results are demonstrated to verify the proposed structure and control method.

A New Z-Source Inverter Topology with High Voltage Boost Ability

  • Trinh, Quoc-Nam;Lee, Hong-Hee
    • Journal of Electrical Engineering and Technology
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    • 제7권5호
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    • pp.714-723
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    • 2012
  • A new Z-source inverter (ZSI) topology is developed to improve voltage boost ability. The proposed topology is modified from the switched inductor topology by adding some more inductors and diodes into inductor branch to the conventional Z-source network. The modulation methods developed for the conventional ZSI can be easily utilized in the proposed ZSI. The proposed ZSI has an ability to obtain a higher voltage boost ratio compared with the conventional ZSI under the same shoot-through duty ratio. Since a smaller shoot-through duty ratio is required for high voltage boost, the proposed ZSI is able to reduce the voltage stress on Z-source capacitor and inverter-bridge. Theoretical analysis and operating principle of the proposed topology are explicitly described. In addition, the design guideline of the proposed Z-source network as well as the PWM control method to achieve the desired voltage boost factor is also analyzed in detail. The improved performances are validated by both simulation and experiment.

Modified Capacitor-Assisted Z-Source Inverter Topology with Enhanced Boost Ability

  • Ho, Anh-Vu;Chun, Tae-Won
    • Journal of Power Electronics
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    • 제17권5호
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    • pp.1195-1202
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    • 2017
  • This paper presents a novel topology named a modified capacitor-assisted Z-source inverter (MCA-ZSI) based on the traditional ZSI. The impedance network of the proposed MCA-ZSI consists of two symmetrical cells coupled with two capacitors with an X-shape structure, and each cell has two inductors, two capacitors, and one diode. Compared with other topologies based on switched ZSI with the same number of components used at impedance network, the proposed topology provides higher boost ability, lower voltage stress across inverter switching devices, and lower capacitor voltage stress. The improved performances of the proposed topology are demonstrated in the simulation and experimental results.