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http://dx.doi.org/10.6113/JPE.2016.16.4.1504

A New Single-Phase Asymmetrical Cascaded Multilevel DC-Link Inverter  

Ahmed, Mahrous (Department of Electrical Engineering, Taif University)
Hendawi, Essam (Department of Electrical Engineering, Taif University)
Publication Information
Journal of Power Electronics / v.16, no.4, 2016 , pp. 1504-1512 More about this Journal
Abstract
This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.
Keywords
Cascaded multilevel inverter; DSPIC microcontroller; MLDC link inverter; SHE; SPWM;
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Times Cited By KSCI : 6  (Citation Analysis)
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1 S. Lu, S. Marieethoz, and K. A. Corzine, “Asymmetrical cascade multilevel converters with noninteger or dynamically changing dc voltage ratios: concepts and modulation techniques,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2411-2418, Jul. 2010.   DOI
2 G. J. Su, “Multilevel DC-link inverter,” IEEE Trans. Ind. Electron., Vol. 41, No. 3, pp. 848–854, May/Jun. 2005.
3 H. Belkamel, S. Mekhilef, A. Masaoud, and M. A. Naeim; “Novel three-phase asymmetrical cascaded multilevel voltage source inverter,” IET Power Electron., Vol. 6, No. 8, pp. 1696-1706, Sep. 2013.   DOI
4 M. M. Hassan, S. Mekhelif, and M. Ahmed, “Three-phase hybrid multilevel inverter with less power electronic components using space vector modulation,” IET Power Electronics, Vol. 7, No. 5, pp. 1256-1265, May 2014.   DOI
5 M. N. Booma and N. Sridhar, “Nine level cascaded H-bridge multilevel DC-link inverter,” International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), pp. 315-320, Mar. 2011.
6 C. Kiruthika, T. Ambika, and R. Seyezhai, “Implementation of digital control strategy for asymmetric cascaded multilevel inverter,” International Conference on Computing, Electronics and Electrical Technologies (ICCEET), pp. 295-300, Mar. 2012.
7 M. N. A. Kadir, S. Mekhilef, and H. W. Ping, “Dual vector control strategy for a three-stage hybrid cascaded multilevel inverter,” Journal of Power Electronics, Vol. 10, No. 2, pp. 155-164, Mar. 2010.   DOI
8 A. L. Batschauer, S. A. Mussa, and M. L. Heldwein; “Three-phase hybrid multilevel inverter based on half-bridge modules,” IEEE Trans. Ind. Electron., Vol. 59, No. 2, pp. 668-678, Feb. 2012.   DOI
9 G. Waltrichand and I. Barbi, “Three-phase cascaded multilevel inverter using power cells with two inverter legs in series,” IEEE Trans. Ind. Electron., Vol. 57, No. 8, pp. 2605-2612, Aug. 2010.   DOI
10 E. Najafi and A. H. M. Yatim, “Design and implementation of a new multilevel inverter topology,” IEEE Trans. Ind. Electron., Vol. 59, No. 11, pp. 4148-4154, Nov. 2012.   DOI
11 M. E. S. Ahmed, M. Orabi, and O. M. Abdelrahim, “Two stages micro grid inverter with high voltage gain for PV applications,” IET Power Electron., Vol. 6, No. 9, pp. 1812-1821, Nov. 2013.   DOI
12 J. Wen and K. M. Smedley, “Synthesis of multilevel converters based on single-and/or three-phase converter building blocks,” IEEE Trans. Power Electron., Vol. 23, No. 3, pp. 1247-1256, May 2008.   DOI
13 H. Iman-Eini, S. Farhangi, J. L. Schanen, and M. Khakbazan-Fard, “A fault-tolerant control strategy for cascaded H-bridge multilevel rectifiers,” Journal of Power Electronics, Vol. 10, No. 1, pp.34-42, Jan. 2010.   DOI
14 P. Lezana, R. Aguilera, and J. Rodriguez, “Fault detection on multicell converter based on output voltage frequency analysis,” IEEE Trans. Ind. Electron., Vol. 56, No. 6, pp. 2275-2283, Jun. 2009.   DOI
15 J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel converter topology with reduced number of power electronic components,” IEEE Trans. Ind. Electron., Vol. 59, No. 2, pp. 655-667, Feb. 2012.   DOI
16 M. R. Subbamma, T. M. Prasad, and V. Madhusudhan, “Comparison of single-phase cascaded and multilevel dc link inverter with pulse width modulation control methods,” International Conference on Sustainable Energy and Intelligent Systems (SEISCON), pp. 229-235, Jul. 2011.
17 D. Andler, S. Kouro, M. Perez, J. Rodriguez, and B. Wu, "Switching loss analysis of modulation methods used in neutral point clamped converters," in IEEE Energy Conversion Congress and Exposition (ECCE), pp. 2565-2571, 2009.
18 M. A. Sayed, M. Ahmed, M. G. Elshaikh, and M. Orabi, “PWM control techniques for single-phase multilevel inverter based controlled DC cells,” Journal of Power Electronics, Vol. 16, No. 2, pp. 498-511, Mar. 2016.   DOI
19 E. Najafi and A. H. M. Yatim, “Design and implementation of a new multilevel inverter topology,” IEEE Trans. Ind. Electron., Vol. 59, No. 11, pp. 4148-4154, Nov. 2012.   DOI
20 B. Kaku, I. Miyashita, and S. Sone, “Switching loss minimised space vector PWM method for IGBT three-level inverter,” IEE Proceedings - Electric Power Applications, Vol. 144, No. 3, pp. 182-192, May 1997.   DOI
21 C. I. Odeh and D. B. N. Nnad, “Single-phase 9-level hybridised cascaded multilevel inverter,” IET Power Electronics, Vol. 6, No. 3, pp. 468-477, Mar. 2013.   DOI
22 J. Rodríguez, L. Morán, J. Pontt, J. L. Hernández, L. Silva, C. Silva, and P. Lezana, “High-voltage multilevel converter with regeneration capability,” IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 839-846, Aug. 2002.   DOI
23 A. Rahmati, M. Arasteh, S. Farhangi, and A. Abrishamifar “Flying capacitor DTC drive with reductions in common mode voltage and stator overvoltage,” Journal of Power Electronics, Vol. 11, No. 4, pp. 512-519, Jul. 2011.   DOI
24 N. Li, Y. Wang, W. Lei, R. Niu, and Z. Wang, “Novel carrier-based PWM strategy of a three-level NPC voltage source converter without low-frequency voltage oscillation in the neutral point,” Journal of Power Electronics, Vol. 14, No. 3, pp. 531-540, May 2014.   DOI
25 W. A. Halim, N. A. Rahim, and M. Azri, “Selective harmonic elimination for a single-phase 13-level TCHB based cascaded multilevel inverter using FPGA,” Journal of Power Electronics, Vol. 14, No. 3, pp. 488-498, May 2014.   DOI
26 K. Corzine and Y. Familiant, “Anew cascaded multilevel H-bridge drive,” IEEE Trans. Power Electron., Vol. 17, No. 1, pp. 125-131, Jan. 2002.   DOI