A New Single-Phase Asymmetrical Cascaded Multilevel DC-Link Inverter

Abstract

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

I. INTRODUCTION

Multilevel inverters (MLIs) represent a significant advancement in the field of power electronics and have recently gained increasing attention because of their advantages over conventional two-level inverters. The most important features of MLI topologies include (a) their high voltage capability and (b) their output voltages that are very near the sinusoidal waveform with low total harmonic distortion (THD), which results in a small output filter. The most popular topologies used in MLIs are the neutral point clamped (NPC) inverters, flying capacitors inverters, and cascaded H-bridge (CHB) inverters [1]-[3].

CHB MLIs are divided into two main groups:(1) symmetric and (2) asymmetric. The symmetric structure of a CHB inverter uses equal and isolated DC voltage sources for each H-bridge cell. A CHB can generate up to the 2n + 1 level of the phase voltage depending on the modulation index (MI); here, “n” is the number of H-bridge inverters per phase. CHB DC sources are usually obtained from three-phase or single-phase diode-bridge rectifiers [3], [4], [5], [13]with the aid of transformers to provide electrical isolation. The construction processes for symmetrical and asymmetrical cascaded H-bridge inverters are almost similar, except that an asymmetrical CHB uses unequal and isolated DC voltage sources [6]. The most popular ratios for DC voltage sources are binary and tertiary ratios, which can generate up to 2(n+1) - 1 and 3n levels of phase voltages, respectively.

Another type of CHB is called the multilevel DC-link inverter. The first multilevel DC-link inverter was introduced in 2003 [7]. As described in [8]-[14], multilevel DC-link inverters have gained significant attention in the last decade. They have been implemented for both single phase and three phases, including in symmetric and asymmetric topologies. Each arm consists of “n” cells connected in series to generate only positive voltage steps of the arm voltage. The basic cell consists of a single DC source and two switches; one switch is connected in series to the DC source, whereas the other switch is connected in parallel to the DC source. Thus, a basic cell is similar to a half-bridge inverter, and it can generate two voltage steps:0V and the DC source voltage. A single arm of “n” cells can generate up to n+1 steps and 2n steps for symmetric and asymmetric topologies, respectively. Therefore, asymmetric topologies offer more advantages than symmetric topologies do because asymmetric topologies reduce the number of switches and gate drive circuits. Generally, a single-phase inverter requires an extra full-bridge circuit known as a folded cascaded or polarity generation circuit [15], [16]. The final output voltage is synthesized by the combination of the input DC voltages of all series-connected units [11], [17]. This topology exhibits modular characteristics because all its units are similar and share the same control strategy. Therefore, defective units can be replaced or bypassed without discontinuing the load by modifying the control method [18], [19].

Several topologies with a fixed neutral point for their DC sources have been proposed and described in the literature. A single-phase MLI with four input sources is proposed in [20]; this topology comprises three DC sources with a fixed neutral point. In [15], Najafi et al. propose the so-called “reversing voltage” MLI topology, which also has a fixed neutral point for its DC sources. These proposed topologies can be considered as one feature of the MLDC link inverter because they comprise two stages: one for voltage level generation and another for polarity generation. Unfortunately, an asymmetrical source configuration (binary or tertiary) cannot be implemented for existing systems because all subtractive and additive combinations of input voltage levels cannot be synthesized.

The present study proposes a new asymmetrical single-phase multilevel topology inverter. This topology is an extension of the MLDC link inverter topology proposed in [7], but it does need to isolate its DC sources. The paper is organized as follows. Section II describes and explains the general block diagram, configuration, and operating principles of the proposed inverter. Section III presents the modulation techniques that can be employed and the generation of switch pulses. Serving as a reference for inverter validity, Section IV provides the PSIM-simulated results and laboratory measurements. These results are used to verify the performance of the proposed MLI, the analysis of which is presented in Section II. Finally, Section V summarizes the proposed inverter concepts presented in the paper.

 

II. OPERATING PRINCIPLES OF PROPOSED TOPOLOGY

Generally, single-phase hybrid multilevel topologies [7], [15], [21]-[23] generate output voltages using two cascaded circuits. The first circuit is called the level generation circuit, and it is responsible for level generating in positive polarity. This circuit normally requires high-frequency switches to generate the required levels, and its switches should feature high switching frequency capability. The second circuit is called the polarity generation circuit (folded cascaded circuit), and it is responsible for generating the polarity of the output voltage. This polarity generation circuit is a simple single-phase H-bridge inverter that is considered as a low-frequency component operating at a line frequency.

Fig. 1 shows the general structure of the proposed hybrid single-phase multilevel inverter. It consists of two circuits, namely, the level generation and polarity generation circuits. The proposed topology offers two main advantages:(1) a high level switch ratio (LSR) [9] resulting from unequal DC voltage values reduces the number of components used; (2) the DC sources are always connected in series (with a common neutral point).The general structure of the level generation circuit is shown in Fig. 1. It consists of “n” cells, each of which comprises a single DC source and two switches. The bottom and top cells are fixed cells with a DC source ratio of 1:2. The repeated cells in the middle are similar and show equal DC sources. Their value is three times the bottom DC source value. The ratio of the bottom DC source to the top one is 1:2 while each repeated cell has a DC value that is three times that of the bottom cell. The generation circuit comprises a total of “Nsw” switches, and it can generate arm voltage levels “NL” for vpN. The load voltage after the polarity circuit is composed of voltage levels (NLP). NL and Nsw can be evaluated using Equs. (1) and (2).

Fig. 1.General structure of the proposed single-phase asymmetrical cascaded inverter.

For n=3, the bus (phase arm) voltage and output load voltage can be calculated in terms of the switch signals from the following equations:

For simplicity, a three-cell (n=3) topology shown in Fig. 2(a) is tested, and its ON/OFF switch operation is given in Table I. This topology comprises seven switching states that can synthesize the 7 levels of the arm voltage vpN and the 13 levels for Vab, as shown in Fig. 2 (b). The direction of the switches SW4-SW7 must be properly chosen to prevent short circuits in the DC sources. Therefore, the two upper switches SW4 and SW5 are connected in the opposite direction to the two lower switches SW6 and SW7, respectively.

Fig. 2.(a) Proposed system configuration for n=3. (b)Output load voltage Vab

TABLE ION/OFF SWITCH OPERATIONS TO GENERATE SEVEN-LEVEL ARM VOLTAGE VPN FOR N= 3

 

III. MODULATION TECHNIQUES FOR THE PROPOSED MLI

The MLI modulation techniques are divided into two categories according to the switching frequency used to operate the inverter switches: (a) low-frequency modulation techniques and (b) pulse-width modulation (PWM) techniques. In this work, both modulation techniques are studied and employed to generate sinusoidal output voltage waveforms, as explained in the following subsections.

A. Low-Frequency Modulation Techniques

Low-frequency modulation techniques are significant because they drastically reduce switching losses [24], [25]. Therefore, such techniques are considered and studied in detail. The three-cell arm inverter shown in Fig. 2 is considered to test the proposed single-phase MLI. The proposed inverter is simulated using a PSIM software package tool. In this method, the selective harmonic elimination (SHE) [3] technique is employed to eliminate the3rd, 5th, 7th, 9th, 11th, and 13th harmonic orders. Therefore, the harmonic contents of the output load waveform begin in the 15thorder. To this end, Fourier transforms for the well-known stepped waveform shown in Fig. 2(b) can be calculated in Equ. (5) as

wherekis the value of the stepped voltage or the lowest DC inverter voltage shown in Fig. 2 and l’ is the number of steps. Based on(5), the normalized magnitudes of the Fourier coefficients are given in Equ. (6).

The studied case of the proposed topology shown in Fig. 2 comprises six steps l = 6. T therefore, with the application of the SHE control technique, each step can cancel one harmonic order. Thus, the 3rd, 5th, 7th, 9th, 11th, and 13th harmonic orders can be cancelled. This can be realized by equating the normalized values calculated from (6) to 0. Then, the solution of the resultant set of nonlinear transcendental equations provides the following values.

θ1 = 7.27°, θ2 = 14.94°, θ3 = 29.44°, θ4 = 40.86°, θ5 = 59.61°, θ6 = 87.55°,

Generating the switch pulses of SW1-SW7 involves six voltages V1-V6, which are compared with a single triangle waveform Vtr1, as shown in Fig. 3(a). Six signals c0 -– c5.are generated for this comparison. These six signals are utilized to generate the pulses of the switches. The voltages V1-V6 are related to the above six angles θ1-θ6 as follows:

, i = 1,2, ..., 6

where θi is in radian and f is the load line frequency (Hz). The triangle carrier has a frequency of 2f and an amplitude of 10, as shown in Fig. 3(a). The pulses of the switches are calculated as follows:

SW1 = c2 - c1 + c5 - c4 +

SW2 = c1 + c4

SW3 = c1 - c0 + c3 - c2 + c5 - c4

SW4 = c1 - c0 + c4 - c3 +

SW5 = c1 - c2 + c4

SW6 = c2

where (+) denotes the logic OR and (−) is generated using the exclusive OR and normal AND gates. Therefore, this method generates switching signals in the same manner as that of the PWM technique without the need to use a lookup table, which requires data storage and extra memory. Fig. 4 shows the load output voltage for different modulation indexes.

Fig. 3.Generating of switch pulses using the SHE technique (two periods from 0 ms to 20ms). (a) Carrier and six constant voltages.(b) ON/OFF signals from top to bottom c0, c1, c2, c3, c4, c5.

Fig. 4.Simulated waveforms of Vab at different modulation indexes for the proposed inverter (voltage step of Vab = k).

B. PWM Technique

This type of modulation technique is implemented by comparing sinusoidal and triangular waveform signals. The comparison produces the Boolean signals required to generate switch control pulses. Thus, the SPWM technique is applied for the proposed topology. It uses six carrier signals with equal amplitudes (Acr) but is shifted by a DC level that is equal to the carrier amplitude. These six carrier signals are compared with one rectified sinusoidal waveform with a peak value (Am) given by Equ. (8). The comparison is shown in Fig. 5(a), and the resulting Boolean output produces the main pulse signals cm1-cm6 shown in Fig. 5(b). After logical processing on cm1-cm6, the switch pulses SW1-SW7 can be generated as specified in (9).

SW1 = (cm2・) + cm5

SW2 = (cm2・)

SW3 = (cm1・) + (cm3・) + (cm5・)

SW4 = (cm1・) + (cm4・) + cm6

SW5 = (cm3・) +

SW6 =

where (+) and (∙) stand for the logic OR and logic AND, respectively. Fig. 6 shows the output voltage waveforms for different modulation indexes. The output voltage levels for this inverter with three cells can vary from 3 levels to 13levels, as shown in Fig. 6.

Fig. 5.Generation of switch pulses using the SPWM technique.

Fig. 6.Simulated waveforms of Vab at different modulation indexes for the proposed inverter (voltage step of Vab = k).

 

IV. SIMULATION AND EXPERIMENTAL RESULTS

The proposed topology is simulated using the PSIM software package tools. A three-cell arm (n=3) shown in Fig. 2(a) is tested to validate the proposed system. However, the proposed topology can be extended to n cells. Power supplies with 40, 80, and 120 V are selected to follow the ratio of 1:2:3. A 2 kHz switching frequency is used in the case of the PWM control method. A single-phase RL load with 370Ω resistance and 0.6H inductor is used.

A small-scale single-phase inverter with the same simulation parameters is built, tested experimentally, and then compared with the simulation results. The inexpensive dspic30F2010 microcontroller is utilized to generate the switching signals. The prototype setup of the proposed MLI is shown in Fig. 7. It includes three DC power supplies, switching devices, measurement tools, the dspic30F2010 controller, and the RL load.

Fig. 7.Experimental setup of the proposed prototype.

First, the system is simulated with the low switching control technique with Am = 5.8. The SHE technique is subsequently employed to cancel lowest-order harmonics (i.e., 3rd-, 5th-, 7th-, 9th-, 11th-,and13th-order harmonics). The output voltage and load current waveforms of the simulation and experimental results are shown in Figs. 8(a) and (b), respectively. The peak voltage is 240V, and the peak current is approximately 0.5A.

Fig. 8.(a) Simulation: load voltage, 100V/div; load current, 1A/div, time, 10ms/div. (b) Experimental: load voltage, 100V/div; load current, 0.5 A/div; time 5, ms/div. (c) Harmonic spectrum of the simulated load voltage. (d) Real-time implementation of the harmonic spectrum of the load voltage.

The harmonic contents start from the 15thharmonic, as shown in Figs. 8(c) and (d), which provide the harmonic spectra of the output load voltages in the simulated and real-time implementation using DSPACE 1007. The THD of the load voltage is approximately 8.27%, which meets the recently published results [3]. Fig. 9 shows the experimental results of the switch pulses for SW1-SW7, in addition to the switches of the H-bridge inverter.

Fig. 9.Experimental results of switch pulses using the SHE control scheme (5ms/ div), (a) switch pulses SW1-SW4, (b) switch pulses SW5-SW7, (c) switch pulses Q1 and Q3.

The performance of the proposed single-phase MLI topology is tested using PWM for MI=0.95. Figs. 10(a) and (b) show the simulation and experimental results of the load voltage and load current, respectively, for the same system parameters. The peak voltage is 240V, and the peak current ≅ 0.5A in the simulation and experiment. The load voltage THD is shown in Fig. 10(c) using DSPACE 1007; the harmonics are centered on the switching frequency and its multiples. Fig. 11 shows the switching pulses for SW1-SW7 switches and the switches of the full-bridge inverter. The simulation and experimental results show a good agreement.

Fig. 10.(a) Simulation: load output voltage and current for SPWM at MI=0.95 (1A/div, 100V/div, 10ms/div), (b) Experimental: load output voltage and current for SPWM at MI=0.95 (1A/div, 100V/div, 5 ms/div), and (c) Real-time implementation of the harmonic spectrum of the load voltage.

Fig. 11.Experimental results of switch pulses using(b) switch pulses SW5-SW7, 2.5ms/div; and(c) switch pulses Q1-Q3, 5ms/div.

The proposed three-cell topology is simulated using PWM to estimate the THD of the load voltage for a wide range of modulation indexes. The result is plotted in Fig. 12. The THD is reduced to approximately less than 10% of the modulation index near unity.

Fig. 12.Modulation index versus load voltage THD.

Table II compares the proposed system with other designs and control methods for the same number of cells per arm.

TABLE IICOMPARISON BETWEEN THE PROPOSED MLI TOPOLOGY AND OTHER SYSTEMS FOR THE SAME NUMBER OF CELLS PER ARM

The comparison involves the number of switching devices, main power diodes, inverter levels, and LSR. The proposed topology shows the second highest level/switch (LSR) ratio among all the other designs. In addition, the proposed topology exhibits a significant advantage because of its fixed neutral point.

 

V. POWER LOSS ANALYSIS

Power losses and inverter efficiency are approximately evaluated. The conduction and switching losses for the switches, including their freewheeling diodes, are considered, whereas the losses of the gate drives and snubber circuits are neglected. The MOSFET IRF9640PBF is used as a power switch. On the basis of the MOSFET data sheet, the following equations are utilized to approximate the proposed inverter losses:

Switch conduction losses,

Diode conduction losses,

Switch switching losses,

Diode switching losses,

where

IM = Switch conduction current

ID = Freewheeling diode forward current

Rds,on = switch ON resistance calculated from the data sheet, 0.75 Ω at 80°

VDF = Diode forward voltage calculated from the data sheet, 1.7V

VMF = Switch blocking voltage

VDF = Diode blocking voltage

Qrr = Body diode reverse recovery charge from the data sheet, 3.6 μC

After calculating the total losses of the inverter, the efficiency is then calculated as follows:

The losses and efficiency of the proposed MLI are evaluated at about 150 W output power and a switching frequency ranging from 1 kHz to 5 kHz. Fig. 13(a) depicts the total conduction losses of both switches and their freewheeling diodes, which represent the dominant losses. Fig. 13(b) shows the total switching losses of both switches and their freewheeling diodes, which are very low in comparison with the conduction losses. This result is attributed to two main factors.(1) In an MLI, the switching of an individual switch or diode is lower than the switching frequency of the whole system.(2) The MOSFET used exhibits extremely low rise and fall times during switching. Fig. 13(c) provides the MLI efficiency under the considered light load. This efficiency changes slightly as the switching frequency varies.

Fig. 13.(a) Total conduction losses (dashed line for diodes and solid line for switches), (b) Total switching losses (dashed line for diodes and solid line for switches), and (c) percentage efficiency.

 

VI. CONCLUSION

A new single-phase asymmetrical MLI with non-isolated DC sources is proposed. The proposed inverter is composed of a level generation circuit and a folded cascaded H-bridge circuit. The operational principles of the proposed inverter are explained in detail. Low switching and PWM control schemes are employed successfully. A generation of pulses and their equations are also provided along with the details of the two control schemes. The LSR of the proposed topology with up to three cells is approximately close to that of existing systems. In addition, the DC sources exhibit a fixed neutral point. The analysis, simulation, and experimental results are provided to validate the proposed system. A dspic30F2010 microcontroller is used to implement the control system and generate MLI switch signals.