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http://dx.doi.org/10.5573/JSTS.2016.16.1.058

Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor  

Angamuthu, Rathinam (Department of EEE, Paavai Engineering College)
Thangavelu, Karthikeyan (Department of EEE, Paavai Engineering College)
Kannan, Ramani (Department of EEE, Paavai Engineering College)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.16, no.1, 2016 , pp. 58-69 More about this Journal
Abstract
This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.
Keywords
Multilevel inverter; APO-PWM; induction motor; total harmonic distortion; topology;
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Times Cited By KSCI : 3  (Citation Analysis)
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