• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.49 no.2
• /
• pp.85-92
• /
• 2000

30 kVA rotating-field type Super-Conducting Generator is built and tested with intensive FE(Finite Element) analysis. The generator is driven by VVVF inverter-fed induction motor. Open Circuit Characteristic(OCC) and Short Circuit Characteristic(SCC) are presented in this paper. Also, the test result under the light load(up to 3.6 kW) are given. From the design stage, 2-D FE analysis coupled with the external circuit has been performed. The external circuit includes the end winding resistance and reactance as well as two dampers. When compared with the test data, the FE analysis results show a very good agreement.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.3
• /
• pp.214-221
• /
• 2021

SiC MOSFETs require a faster and more reliable short-circuit protection circuit than conventional methods due to narrow short-circuit withstand times. Therefore, this research proposes a short-circuit protection circuit using a current-sensing circuit based on Rogowski coil. The method of designing the current-sensing circuit, which is a component of the proposed circuit, is presented first. The integrator and input/output filter that compose the current-sensing circuit are designed to have a wide bandwidth for accurately measuring short-circuit currents with high di/dt. The precision of the designed sensing circuit is verified on a double pulse test (DPT). In addition, the sensing accuracy according to the bandwidth of the filters and the number of turns of the Rogowski coil is analyzed. Next, the entire short-circuit protection circuit with the current-sensing circuit is designed in consideration of the fast short-circuit shutdown time. To verify the performance of this circuit, a short-circuit test is conducted for two cases of short-circuit conditions that can occur in the half-bridge structure. Finally, the short-circuit shutdown time is measured to confirm the suitability of the proposed protection circuit for the SiC MOSFET short-circuit protection.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.3
• /
• pp.401-417
• /
• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.5
• /
• pp.82-89
• /
• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.49-56
• /
• 2005

In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.882-885
• /
• 2011

This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.

• Proceedings of the KIEE Conference
• /
• 1999.07c
• /
• pp.1186-1188
• /
• 1999

When we perform the test related to the power distribution system such as artificial fault test, protective coordination test, distribution automation test in short length test line, Lumped Constant Circuit, a kind of variable impedance, should be attached to the test line in order to make it equivalent to a real line in length electrically. In this paper we designed the positive sequence and zero sequence Lumped Constant Circuit with optimized inductor and resister for the modification of long, 16km, distribution line, when they are attached to the short, 4km, distribution test line.

• ETRI Journal
• /
• v.31 no.2
• /
• pp.209-214
• /
• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• Proceedings of the KIEE Conference
• /
• summer
• /
• pp.554-556
• /
• 2004

Testing capacity of KERI synthetic short-circuit testing facilities has been upgraded to fulfill the requirements up to 550kV 63kA, 1-break circuit breaker ratings. Specially the current capacity was increased 50kA to 63kA and the full type test of 362kV 63kA circuit breaker(1-break) was firstly completed in domestic. UP to now, domestic manufacturers have depended on the foreign testing laboratory for performance verification of newly designed products. This paper introduces the summary of the increased short-circuit testing facilities, the testing techniques and its results for the making and breaking performance of 362kV, 63kA circuit breaker which was Performed according to IEEE C37.06(1999) used in North America.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.2
• /
• pp.10-21
• /
• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.