• 전자공학회논문지 IE
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• v.44 no.2
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• pp.14-20
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• 2007

This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.367-373
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• 2001

A programmable A/D converter is designed with 8 N and P channel MOSFETs, respectively. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a 1.2 ${\mu}{\textrm}{m}$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10m Volt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, 37㎽ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.29-37
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• 2006

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.10
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• pp.3905-3910
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• 2010

In this paper, a 3rd-order Chebyshev current-mode filter in 1.8V-$0.18{\mu}m$ CMOS parameter is designed. The core circuit of the current-mode filter is composed with the proposed voltage-controlled frequency tunable current-mode integrator. Using the proposed current-mode integrator, the cutoff frequency of the filter can be controlled and also total power consumption can be reduced. HSPICE simulation results show the cutoff frequency of the filter is controlled between 1.2MHz and 10.1MHz, and the power consumption is 2.85mW at Vdd=1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of the Korea Computer Industry Society
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• v.2 no.10
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• pp.1253-1260
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• 2001

In this paper, a new voltage-controlled tunable analog active element for low-voltage applications and information protection is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transconductance is increased than that of the conventional element. And then these results are verified by the $0.25\mutextrm{m}$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42㏈ and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.753-758
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• 2002

In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1172-1177
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• 2008

To compensate voltage error of the channel selecting filter, a current comparison type voltage tuning circuit is designed. Because the proposed current comparison type voltage tuning circuit is not need to attach another subcircuit, the chip size can be reduced, therefore the proposed circuit is very useful in the low voltage and low power channel filter. We used three channels including bluetooth communication system as application circuits of the proposed tuning circuit. As the results of HSPICE simulation using $0.18{\mu}m$ CMOS technology verify that the proposed tuning circuit respectively can be operated in $12{\mu}s$, $13{\mu}s$ and $15{\mu}s$ in three channel.