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Effective Power/Ground Network Design Techniques to suppress Resonance Effects in High-Speed/High-Density VLSI Circuits  

Ryu Soon-Keol (Dept. of Electrical & Computer Engineering, Hanyang University)
Eo Yung-Seon (Dept. of Electrical & Computer Engineering, Hanyang University)
Shim Jong-In (Dept. of Electrical & Computer Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.7, 2006 , pp. 29-37 More about this Journal
Abstract
This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.
Keywords
resonance; ground bounce; on-chip decoupling capacitor; signal integrity;
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