• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.850-853
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• 2005

This paper presents issues of display hardware architecture, relating to memory, display driver IC architecture, and chip-to-chip interface. To achieve a low power and low cost mobile phone, not only the display architecture must be carefully selected, but also the driver-ICs optimized to accommodate the different modes of operation found in typical handheld devices. The technique of forming a photo sensor in each pixel using TFT and display module architecture are developed to add multi functions in display such as fingerprint recognition, image scanning, and integrated touch screen. Detailed architectures of IC partitioning, high-speed serial interface, D/A converter, and multi functions such as fingerprint recognition and image scanning using photo sensors are important to a power optimized system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.291-292
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• 2014

High-speed video transmission modes of master bridge IC are implemented, which supports MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) standard. MIPI DSI master bridge IC sends RGB data and various commands to display module (slave) in order to test it. The master bridge IC consists of buffers storing video data of two lines, packet generation block, and D-PHY layer that distributes packets to data lanes and transmits them to slave. In addition, it supports four bpp (bit per pixel) formats and three transmission modes including Burst and Non-Burst (Sync Events, Sync Pulses types). The designed bridge IC is verified by RTL simulations showing that it functions correctly for various operating parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.155-167
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• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1152-1156
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• 2003

For pneumatic valve system control, we need a serial data transmission system with high speed and reliability for information interchange between main computer and I/O devices. This paper presents a set of design techniques for a data communication system that is mainly used for pneumatic valve system control. For this purpose, we first designed hardware modules for an interface between central control module and local node that handles the operation of solenoid control valves. in addition, we developed a communication protocol for construction of rs-485 based multi-drop network and this protocol is basically designed with a kind of polling technique. Finally we evaluated performance of the developed system. the field test results show that, even under high noise environment, the data transmission of 375kbps rate is possible up to 1,500meter without using repeater. In addition, the system developed in this research is easily to be extended for a communication network because of its modular structure.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.1
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• pp.69-74
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• 2010

Now the CAN(controller Area Network) is using electronic modules as a serial communication which is very robust to noise. Especially the CAN is using for automotive part that very popular in which automotive electronic control module, engine controller unit, sensor modules, etc. but the CAN has the order of priority to linking node and also has fault confinement so using in these features that is applied to in factory automation product line. The CAN communication is basically very robust to electric noise so varied applying to others part. In this paper, we suggest to CAN interface for embedded system that is possible for error detection using two CAN nodes on Hi-speed, full-CAN.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.494-503
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• 2003

The IEEE 1394 High Speed Serial Bus is a versatile, high-performance, and low-cost method of promoting interoperability between all types of A/V and computing devices. IEEE 1394 provides two transfer modes: asynchronous mode for best effort service and isochronous mode for best effort service with bandwidth reservation. This paper shows the bus performance and compared the transfer odes first at the link level and then at the application level. For the application level performance, we analyze the bus systems with fixed and adaptive interfaces, applied between the upper layer and the 1394 layer, using polling systems. Also we verifies the analysis models with simulation studies. Based on our analysis, we conclude that the adaptive interface reduces the bus access time and so increases the bus utilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of Satellite, Information and Communications
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• v.9 no.1
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• pp.13-16
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• 2014

In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.499-500
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• 2008

기존 칩들 사이에 사용되는 인터페이스는 많은 선을 사용하여 EMI문제를 발생시키고 PCB에 많은 중간을 차지한다. 이를 해결하기 위하여 개발된 UniPro는 적은 선으로 빠른 통신속도를 지원하며 저전력 통신을 위하여 D-PHY와 함께 사용된다. 본 논문에서는 MIPI 규격의 UniPro를 설계하였다. 설계된 UniPro는 4개의 데이터 레인과 1개의 클럭 레인으로 구성하여 디바이스 사이의 데이터 및 제어신호를 전송 가능하다. 또한 낮은 전력소모를 위하여 전원 관리 장치를 추가하였으며 수신한 데이터의 에러검출이 가능하도록 설계하여 신뢰도를 높였다. 설계된 인터페이스는 5,160 Gate크기이며 속도는 98MHz이다.