• Transactions of the Korean hydrogen and new energy society
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• v.23 no.4
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• pp.373-381
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• 2012

To determine the performance characteristics of motorcycle engine using biogas for practical use, the intake system of a 110 cc motorcycle engine is properly modified to operate with biogas as a fuel. Biogas is a potentially renewable fuel for replacing gasoline in future, but it has high percentage of $CO_2$ that could lead to slow the burning rate of biogas-air mixture and cause instability in combustion. Thus, the performance characteristics of biogas-fueled motorcycle engines could be different from those of gasoline motorcycle engines. In this paper, the important parameters of performance characteristics (such as: power output, thermal efficiency, fuel consumption, exhaust emission,${\cdots}$) of biogas-fueled motorcycle engine are studied and estimated with change of engine speed and load. The obtained results when operating with biogas are used to compare with that of gasoline fuel under the same operating conditions. Engine speed in the experimental is changed from 1500 rpm (idle-mode) up to 3500 rpm by a step of 500 rpm. Engine load is changed from zero to maximum load with the help of an exciting voltage device from generator-type dynamometer. The experimental results show that the tested engine operated with richer biogas-air mixture than that of gasoline-air mixture under the same test conditions. Biogas-fueled engine gives a higher fuel consumption and lower thermal efficiency under the same power output. Brake thermal efficiency of biogas engine is found to be about 3% lower than gasoline-fueled motorcycle engine for whole range of speed. Exhaust emission of biogas-fueled motorcycle engine (such as: CO, HC) is found to be lower than the limitation level of the emission standards of Vietnam for motorcycle engines (CO <4.5% HC <1200 ppm).

• Journal of IKEEE
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• v.18 no.4
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• pp.544-551
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• 2014

This paper suggests an algorithm to measure low-level radiation by radiation measuring devices, and the other algorithm to improve reaction speed of the device to better respond to dramatic changes in radiation amount. The former algorithm to improve the accuracy of measuring low-level radiation takes advantage of a dual window radiation measurement method which is based on accumulated average of pulses gathered by a radiation measuring sensor. The latter algorithm is to enhance reaction speed of a measuring device to more sensitively react to dramatic changes in radiation amount by adopting a dual window radiation measurement method which analyzes data patterns newly put into for six seconds. To verify the suggested algorithms, a hardware-which consists of sensor and high-voltage generator, controller, charger and power supply circuit, wireless communication part, and display part-was used. Tests conducted on the dual window radiation measurement method as used in the suggested algorithm have proved that accuracy improves to measure low-level radiation of 5uSv/h, and linearity also gets better. Other tests were conducted to see whether the suggested algorithm enhances the reaction speed of a radiation measuring device so that the device responds better to dramatically changing radiation amount. The experimental results have shown meaningful changes in numbers after six seconds. Therefore, the conclusions are made that the algorithm enhances the reaction speed of the device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.5
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• pp.381-388
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• 2014

Our aim was to simulate ocean waves in a small-size wave flume and observe the motion of a cylindrical floating body placed in an offshore environment. To precisely visualize the oscillation of the body, a set of light-emitting diode illuminators and high-speed charge-coupled device camera were installed in the flume. Spectral analysis was performed of the movement of the floating body. The wave generator and absorbers worked well to simulate stable regular waves. As the period of the oncoming waves changed, the movement of the floating body substantially differed when tethered to a tension-leg mooring cable. In particular, when connected to the tension-leg mooring cable, the natural frequency of the floating body suddenly appeared at 0.391 Hz as the wave period was increased.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.926-934
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• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• 연구논문집
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• s.27
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• pp.87-99
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• 1997

Present paper describes on/off design performance of a 50KW turbogenerator gas turbine engine for hybrid vehicle application. For optimum design point selection, relevant parameter study is carried out. The turbogenerator gas turbine engine for a hybrid vehicle is expected to be designed for maximum fuel economy, ultra low emissions, and very low cost. Compressor, combustor, turbine, and permanent-magnet generator will be mounted on a single high speed (82,000 rpm) shaft that will be supported on air bearings. As the generator is built into the shaft, gearbox and other moving parts become unnecessary and thus will increase the system's reliability and reduce the manufacturing cost. The engine has a radial compressor and turbine with design point pressure ratio of 4.0. This pressure ratio was set based on calculation of specific fuel consumption and specific power variation with pressure ratio. For the given turbine inlet temperature, a rather conservative value of $1100^\circK$ was selected. Designed mass flow rate was 0.5 kg/sec. Parametric study of the cycle indicates that specific work and efficiency increase at a given pressure ratio and turbine inlet temperature. Off design analysis shows that the gas turbine system reaches self operating condition at N/$N_{DP}$ = 0.53. Bleeding air for turbine stator cooling is omitted considering low TIT and for a simple geometric structure. Various engine performance simulations including, ambient temperature influence, surging at part load condition. Transient analysis were performed to secure the optimum engine operating characteristics. Surge margin throughout the performance analysis were maintained to be over 80% approximately. Validation of present results are yet to be seen as the performance tests are scheduled by the end of 1998 for comparison.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.93-101
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• 2010

In this paper we generate Gold-sequence by using M-sequence which is made by two primitive polynomial of GF(2). Generally M-sequence is generated by linear feedback shift register code generator. Here we show that this matrix of appropriate permutation has Hadamard matrix property. This matrix proves that Gold-sequence through two M-sequence and additive matrix of one column has one of major properties of Hadamard matrix, orthogonal. and this matrix show another property that multiplication with one matrix and transpose matrix of this matrix have the result of unit matrix. Also M-sequence which is made by linear feedback shift register gets Hadamard matrix property mentioned above by adding matrices of one column and one row. And high-speed conversion is possible through L-matrix and the S-matrix.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.22-27
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• 2009

In this paper, an automatic functional inspection system EVT (Emulated Vision Tester) for LCD drive module PCB has been proposed and implemented. Typical automatic inspection system such as probing methods and vision-based systems are widely known and used, however, there exist undetectable defects due to critical timing factors which they may miss to catch from LCD equipments. Especially typical vision-based systems have inconsistency on acquisition of images so that distinction between gray scales can be difficult which results in low level of performance and reliability on the inspection results. The proposed EVT system is pure hardware solution. It directly compares pattern signals from a pattern generator to output signals from LCD drive module. It also inspects variety of analog signals such as voltage, resistance, wave forms and so forth. The EVT system not only shows high performance in terms of reliability and processing speed but reduces costs on inspection and maintenance. Also, full automation of entire production line can be realized when EVT is applied in in-line inspection processes.