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http://dx.doi.org/10.13089/JKIISC.2004.14.4.123

FPGA Implementation and Performance Analysis of High Speed Architecture for RC4 Stream Cipher Algorithm  

최병윤 (동의대학교)
이종형 (동의대학)
조현숙 (한국전자통신연구원)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.14, no.4, 2004 , pp. 123-134 More about this Journal
Abstract
In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.
Keywords
RC4; Stream Cipher; WEP; Pseudo Random Number Generator;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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