• 제목/요약/키워드: high cut-off frequency

검색결과 159건 처리시간 0.026초

액티브 스너버를 이용한 고주파 용접기 컨버터 개발 (Development of Converter for High Frequency Welding Machines using Active Snubber)

  • 신준영;이재민;최승원;이준영
    • 전력전자학회논문지
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    • 제21권4호
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    • pp.351-355
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    • 2016
  • Welding machines are high-capacity systems used in a low-frequency range using IGBT. As their system is similar to a large transformer, most welding machines suffer a great loss because of hard switching and vast leakage inductance. A voltage-balancing circuit is designed to overcome these shortcomings. This circuit can reduce the transformer size by making it into a high frequency and reducing the input voltage by half and by adopting a serial structure that connects two full-bridges in a series to use a MOSFET with a good property at high frequency. In addition, a Schottky diode is used in the primary rectifier to overcome the low efficiency of most welding machines. To use the Schottky diode with a reliably relatively low withstanding voltage, an active snubber is adopted to effectively limit the ringing voltage of the diode cut-off voltage.

온도변화에 따른 GaAs MESFET의 주파수 특성에 관한 연구 (A Study on Frequency Response of GaAs MESFET with different Temperatures)

  • 정태오;박지홍;안형근;한득영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.550-553
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    • 2001
  • In this study, unity current gain frequency f$\_$T/ of GaAs MESFET is predicted with different temperatures up to 400 $^{\circ}C$. Temperature dependence parameters of the device including intrinsic carrier concentration n$\_$i/ effective mass, depletion width are considered to be temperature dependent. Small signal parameters such as gate-source, gate dran capacitances C$\_$gs/ C$\_$gd/ are correlated with transconductance g$\_$m/ to predict the unity current gain frequency. The extrinsic capacitance which plays an important roles in high frequency region has been taken into consideration in evaluating total capacitance by using elliptic integral through the substrate. From the results, f$\_$T/ decreases as the temperature increases due to the increase of small signal capacitances and the mobility degradation. Finally the extrinsic elements of capacitances have been proved to be critical in deciding f$\_$T/ which are originated from the design rule of the device.

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저압배선계통에서 직렬아크의 검출에 관한 연구 (A Study on the Series Arc Detection in Low-voltage Wiring Systems)

  • 김일권;박대원;최수연;박찬용;김황국;길경석
    • 한국전기전자재료학회논문지
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    • 제21권2호
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    • pp.182-187
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    • 2008
  • This paper dealt with the detection algorithm of series arcing, which is a cause of electric fires in low-voltage wiring systems. To find the distinguished electrical features of series arc, we simulated series arcing by the arc generator specified in UL1699. An electric heater, an inverter-controlled vacuum cleaner, and a phase-controlled incandescent lamp were used as loads to generate series arcing. A high-pass filter (HPF) with the low cut-off frequency of 3 kHz at -3 dB was fabricated and applied to separate the series arc signal from the AC voltage source. The experiment showed that the high frequency signal generates randomly during series arcing, and the phase-controlled incandescent lamp produces high frequency pulses even in normal state. In this case, the magnitude, the width, and the randomness of high frequency signal should be analyzed to estimate series arcing precisely.

대역폭 조정 가능한 다중 생체 신호 처리용 대역 통과 필터 설계 (A Tunable Band-Pass Filter for Multi Bio-Signal Detection)

  • 정병호;임신일;우덕하
    • 전기전자학회논문지
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    • 제15권1호
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    • pp.57-63
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    • 2011
  • 본 논문에서는 대역폭 조정이 가능한 다중 생체 신호 처리용 대역 통과 필터 회로에 관한 것이다. 일반적인 대역 통과 필터는 출력 단에 연결되는 커패시터 배열의 값을 조절하여 고역 -3dB 차단 주파수를 결정한다. 하지만 본 논문에서 제안하는 대역 통과 필터 회로는 커패시터 대신에, 증폭기에 사용되는 바이어스 전압을 통해 증폭기의 트랜스 컨덕턴스 값을 조절하여 차단 주파수를 조절한다. 이러한 방법은 기존의 방식보다 칩 면적을 최소한 1/10로 줄일 수 있어 저면적 설계가 가능하다. 조정 가능한 고역 -3dB 차단 주파수의 대역은 100Hz에서 1KHz이며 사용된 공정은 0.18um CMOS 표준 공정이다. 저 전력 설계를 위해 회로는 서브 스레쉬 홀드 영역에서 동작하며 공급전압은 1V이고, 회로의 총 전류 소모는 1uA이다.

부분 채널도핑된 GaAs계 이중이종접합 전력FET의 선형성 증가 (Linearity Enhancement of Partially Doped Channel GaAs-based Double Heterostructure Power FETs)

  • 김우석;김상섭;정윤하
    • 대한전자공학회논문지SD
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    • 제39권1호
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    • pp.83-88
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    • 2002
  • HFET 소자의 선형성과 게이트-트레인 항복특성을 향상시키기 위해 부분채널 도핑된 Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As/Al/sub 0.25/Ga/sub 0.75/As 이종접합 구조를 갖는 FET를 제안하였다. 제안된 HFET는 게이트 전극 아래로 도핑되지 않은 AlGaAs 진성공급층을 두어 -2OV 의 높은 항복전압을 얻었다. 또한 소자의 InGaAs 채널에 부분 도핑을 실시하여, 균일 채널 도핑을 실시한 경우보다 향상된 선형성을 유도하였고, 2차원 전산모사 견과와 제작 및 측정결과를 통해 선형성의 향상을 확인하였다. 본 실험에서 제안된 HFET소자는 DC측정 결과와 고주파측정 결과 모두에서 기존의 FET소자들에 비해 향상된 선형성을 나타내었다.

Experimental test on bridge jointed twin-towered buildings to stochastic wind loads

  • Ni, Z.H.;He, C.K.;Xie, Z.N.;Shi, B.Q.;Chen, D.J.
    • Wind and Structures
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    • 제4권1호
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    • pp.63-72
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    • 2001
  • This paper presents results of a study on wind loads and wind induced dynamic response of bridge jointed twin-towered buildings. Utilizing the high-frequency force balance technique, the drag and moment coefficients measured in wind tunnel tests, and the maximum acceleration rms values on the top floor of towers, are analyzed to examine the influence of building's plan shapes and of intervals between towers. The alongwind, acrosswind and torsional modal force spectra are investigated for generic bridge jointed twin-towered building models which cover twin squares, twin rhombuses, twin triangles, twin triangles with sharp corners cut off, twin rectangles and individual rectangle with the same outline aspect ratio as the twin rectangles. The analysis of the statistical correlation among three components of the aerodynamic force corroborated that the correlation between acrosswind and torsional forces is significant for bridge jointed twin-towered buildings.

Different Criteria for the Definition of Insulin Resistance and Its Relation with Dyslipidemia in Overweight and Obese Children and Adolescents

  • Nogueira-de-Almeida, Carlos Alberto;de Mello, Elza Daniel
    • Pediatric Gastroenterology, Hepatology & Nutrition
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    • 제21권1호
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    • pp.59-67
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    • 2018
  • Purpose: to compare cut off points corrected for age and gender (COOP) with fixed cut off points (FCOP) for fasting plasma insulin and Homeostatic model assessment-insulin resistance (HOMA-IR) for the diagnosis of IR in obese children and adolescents and their correlation with dyslipidemia. Methods: A multicenter, cross-sectional study including 383 subjects aged 7 to 18 years, evaluating fasting blood glucose, plasma insulin, and lipid profile. Subjects with high insulin levels and/or HOMA-IR were considered as having IR, based on two defining criteria: FCOP or CCOP. The frequency of metabolic abnormalities, the presence of IR, and the presence of dyslipidemia in relation to FCOP or CCOP were analyzed using Fisher and Mann-Whitney exact tests. Results: Using HOMA-IR, IR was diagnosed in 155 (40.5%) and 215 (56.1%) patients and, using fasting insulin, 150 (39.2%) and 221 (57.7%), respectively applying FCOP and CCOP. The use of CCOP resulted in lower insulin and HOMA-IR values than FCOP. Dyslipidemia was not related to FCOP or CCOP. Blood glucose remained within normal limits in all patients with IR. There was no difference in the frequency of IR identified by plasma insulin or HOMA-IR, both for FCOP and CCOP. Conclusion: The CCOP of plasma insulin or of HOMA-IR detected more cases of IR as compared to the FCOP, but were not associated with the frequency of dyslipidemia. As blood glucose has almost no fluctuation in this age group, even in the presence of IR, fasting plasma insulin detected the same cases of IR that would be detected by HOMA-IR.

Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

  • Gupta, Ritesh;Kaur, Ravneet;Aggarwal, Sandeep Kr;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권1호
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    • pp.66-77
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    • 2010
  • Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

Partial SOI 기판을 이용한 고속-고전압 Smart Power 소자설계 및 전기적 특성에 관한 연구 (Design of a New Smart Power ICs based on the Partial SOI Technology for High Speed & High Voltage Applications)

  • 최철;구용서;안철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.249-252
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    • 2000
  • A new Smart rower IC's based on the Partial SOI technology was designed for such applications as mobile communication systems, high-speed HDD systems etc. A new methodology of integrating a 0.8${\mu}{\textrm}{m}$ BiCMOS compatible Smart Power technology, high voltage bipolar device, high speed SAVEN bipolar device, LDD NMOSFET and a new LDMOSFET based on the Partial SOI technology is presented in this paper. The high voltage bipolar device has a breakdown voltage of 40V for the output stage of analog circuit. The optimized Partial SOI LDMOSFET has an off-state breakdown voltage of 75 V and a specific on- resistance of 0.249mΩ.$\textrm{cm}^2$ with the drift region length of 3.5${\mu}{\textrm}{m}$. The high-speed SAVEN bipolar device shows cut-off frequency of about 21㎓. The simulator DIOS and DESSIS has been used to get these results.

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새로운 구조의 고속-고내압 SOI Smart Power 소자 설계에 관한 연구 (A Study on the Design of the New Structural SOI Smart Power Device with High Switching Speed and Voltage Characteristics)

  • 원명규;구용서;안철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.239-242
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    • 1999
  • In this paper, we report the process/device design of high-speed, high-voltage SOI smart power IC for mobile communication system, high-speed HDD system and the electronic control system of automobiles. The high voltage LDMOS with 70V breakdown voltage under 0.8${\mu}{\textrm}{m}$ design rule, the high voltage bipolar with 40V breakdown voltage for analog signal processing, the high speed bipolar with cut-off frequency over 20㎓ and LDD NMOS for high density were proposed and simulated on a single chip by the simulator DIOS and DESSIS. And we extracted the process/device parameters of the simulated devices.

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