• Title/Summary/Keyword: guard ring

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Investigation of Curvature Effect on Planar InP/InGaAs Avalanche Photodiodes for Edge Breakdown Suppression (경계항복 억제를 위한 평판형 InP/InGaAs 애벌랜치 포토다이오드의 곡률 효과 분석)

  • 이봉용;정지훈;윤일구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.206-209
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    • 2002
  • With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

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Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter

  • Cui, Zhi-Yuan;Kim, Nam-Soo;Lee, Hyung-Gyoo;Kim, Kyoung-Won
    • Transactions on Electrical and Electronic Materials
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    • v.8 no.1
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    • pp.21-25
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    • 2007
  • A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

Analysis on the Diagnosis Characteristics of Electrical Insulating Oil for Power Transformer with 3-terminal Capacitive Sensor (3전극형 전기용량 센서를 이용한 변압기 절연유의 열화감지특성 평가)

  • Kim, Ju-Han;Seo, Pan-Seok;Kim, Pil-Hwan;Kim, Myung-Hwan;Park, Hung-Seok;Han, Sang-Ok
    • Proceedings of the KIEE Conference
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    • 2004.11d
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    • pp.89-92
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    • 2004
  • This paper described the capacitive sensor for the diagnosis of deterioration of electrical insulating oils applying guard-ring type the 3-terminal electrodes. To measure stable capacitance of the sensor and to determine the design factors of the sensor, we utilized computational analysis, FEM software. This capacitive sensor discern the extent of deterioration measuring relative permittivity of electrical insulating oils. The result of measuring numerous sample, mineral oils, as serviced year, we confirmed an increase in relative permittivity of oils. Moreover, we confirmed the superior characteristics of the sensor as a species, aged pattern of oils and operating temperature.

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Characteristics of the Suppressed Sidewall Injection Magnetotransistor using a CMOS Process (CMOS 공정에 의한 Suppressed Sidewall Injection Magnetotransistor의 특성)

  • Song, Youn-Gui;Choi, Young-Shig;Kim, Nam-Ho;Ryu, Ji-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.10
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    • pp.1029-1033
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    • 2004
  • In this paper, we propose a new Suppressed Sidewall Injection Magnetotransistor(SSIMT) architecture, which allows to overcome the restriction of the standard CMOS technology and achieve high linearity. The proposed SSIMT is designed based on the Hynix 0.6 um standard CMOS technology. The fabricated SSIMT has been experimentally verified. The SSIMT shows that the change of collector current is extremely linear as a function of the magnetic induction at $I_{B}$ =500$\mu$A, $V_{CE}$ =2V and VSE =5 V. The relative sensitivity is up to 120 %/T. The magnetic conversion offset is about 79 mT with 30.5 %/T relative sensitivity. The nonlinearity of the fabricated SSIMT is measured about 1.4 %.%.

EM Coupling Effect of sprint inductors by isolation methode in standard CMOS process (Spiral 인덕터 간 격리방법에 따른 Electromagnetic 커플링 효과)

  • Choi, Moon-Ho;Kim, Han-Seok;Jung, Sung-Il;Kim, Yeong-Seuk
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.91-92
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    • 2005
  • The electromagnetic coupling effect in standard CMOS process is simulated and evaluated. EM coupling transfer characteristic between planar spiral inductors by isolation methode in standard CMOS have simulated and measured. Measurement results show that suppression of EM coupling effect by ground guardring. The evaluated structures are fabricated 1P5M(one poly, five metal) 0.25um standard CMOS process. These measurement results provide a isolation design guidelines in standard CMOS process for Rf coupling suppression.

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The Properties of Ar RF Plasma Using 1- and 2-dimensional Model (1,2차 모델링을 이용한 Ar RF 플라즈마의 응답 특성)

  • 박용섭;정해덕
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.8
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    • pp.622-628
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    • 2001
  • We developed 1- and 2-dimensional fluid model for the analysis of a capacitively coupled Ar RF(Radio Frequency) glow discharge. This discharge is in pure Ar gas at the pressure 100[mTorr], frequency 13.56[MHz] and voltage amplitude 120[V}. This model is based on the equations of continuity and electron energy conservation coupled with Poison equation. 2-dimensional model is simulated on the condition of GEC(Gaseous Electronic Conference cell). The geometry of the discharge chamber and the electrodes used in the model is cylindrically simmetric; tow cylinders for the electrodes are surrounded by the grounded chamber. It is shown that 1-dimensional model is very useful on the understanding of RF glow discharge property and of the movement of charged particles. 2-dimensional model predicts off-axis maximum structure as in the experiments and has the results in qualitatively and quantitatively good agreement with the experiments. Effects of dc self-bias voltage, guard ring and reactor geometry is discussed.

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Fabrication of Schottky diodes for RFID tag integration using Standard $0.18{\mu}m$ CMOS process (RFID tag 집적화를 위한 $0.18{\mu}m$ 표준 CMOS 공정을 이용한 쇼트키 다이오드의 제작)

  • Shim, Dong-Sik;Min, Young-hun
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.591-592
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    • 2006
  • Schottky diodes for Radio-frequency identification (RFID) tag integration on chip were designed and fabricated using Samsung electronics System LSI standard $0.18{\mu}m$ CMOS process. Schottky diodes were designed as interdigitated fingers array by CMOS layout design rule. 64 types of Schottky diode were designed and fabricated with the variation of finger width, length and numbers with a $0.6{\mu}m$ guard ring enclosing n-well. Titanium was used as Schottky contact metal to lower the Schottky barrier height. Barrier height of the fabricated Schottky diode was 0.57eV. DC current - voltage measurements showed that the fabricated Schottky diode had a good rectifying properties with a breakdown voltage of -9.15 V and a threshold voltage of 0.25 V.

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I-V Characteristics of SAGCM APD by Varing Guard-Ring Depth (SAGCM APD 에서의 가드링 형태에 따른 I-V 특성 연구)

  • 현경숙;백영미
    • Proceedings of the Optical Society of Korea Conference
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    • 2003.07a
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    • pp.100-101
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    • 2003
  • 본 논문은 초고속 광통신용 검출기로 사용되고 있는 InP/InGaAs Avalanche Photodiode (APD)에 대한 연구로서 구조 변화에 따른 APD의 특성에 대해 연구하였다. 채택된 APB의 기본 구조는 Separated Absorption, Grading, Charge and Multiplication (SAGCM)구조로 u-InP 의 두께 3.5$\mu\textrm{m}$에~2.9$\mu\textrm{m}$ 만큼 Zn diffusion 하였으며, u-InGaAs 의 흡수층 두께는 0.8$\mu\textrm{m}$ 로 하였다. charge sheet 층의 도핑 농도는 ~ 3.5 $\times$ 10/sup 12//cm/sup 2/ 이고, 전극 구조는 back side illumination type이다. (중략)

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A Study of SiC Trench Schottky Diode with Tilt-Implantation for Edge Termination (Edge Termination을 위해 Tilt-Implantation을 이용한 SiC Trench Schottky Diode에 대한 연구)

  • Song, Gil-Yong;Kim, Kwang-Soo
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.214-219
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    • 2014
  • In this paper, the usage of tilt-implanted trench Schottky diode(TITSD) based on silicon carbide is proposed. A tilt-implanted trench termination technique modified for SiC is proposed as a method to keep all the potentials confined in the trench insulator when reverse blocking mode is operated. With the side wall doping concentration of $1{\times}10^{19}cm^{-3}$ nitrogen, the termination area of the TITSD is reduced without any sacrifice in breakdown voltage while potential is confined within insulator. When the trench depth is set to 11um and the width is optimized, a breakdown voltage of 2750V is obtained and termination area is 38.7% smaller than that of other devices which use guard rings for the same breakdown voltage. A Sentaurus device simulator is used to analyze the characteristics of the TITSD. The performance of the TITSD is compared to the conventional trench Schottky diode.

Ship Collision Avoidance Support Model in Close Quarters Situation (II) (근접상황 선박충돌회피지원모델에 관한 연구(II))

  • Yang Hyoung-Seon;Yea Byeong-Deok
    • Journal of Navigation and Port Research
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    • v.29 no.10 s.106
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    • pp.827-832
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    • 2005
  • In this paper, as a fundamental study of ship collision avoidance supporting system in close quarters situation, we propose ship collision avoidance support model for decreasing ship collision accidents those have occurred due to navigator's unsuitable maneuvering in close encounter. This model will effectively support maneuvering for collision avoidance through displaying the feasible area and the method of collision avoidance using own ship's turning characteristic about action of target ship's keeping course and velocity.