• 반도체디스플레이기술학회지
• /
• 제5권1호
• /
• pp.21-25
• /
• 2006

To improve the performance of organic thin film transistor, we investigated the properties of gate insulator's surface according to the leakage current by I-V measurement. The surface was treated by the dilute n-octadecyltrichlorosilane solution. The alkyl group of n-octadecyltrichlorosilane induced the electron tunneling and the electron tunneling current caused the breakdown at high electric field, consequently shifting the breakdown voltage. The 0.5% sample with an electron-rich group was found to have a large leakage current and a low barrier height because of the effect of an energy barrier lowered by, thermionic current, which is called the Schottky contact. The surface properties of the insulator were analyzed by I-V measurement using the effect of Poole-Frankel emission.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.428-431
• /
• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권3호
• /
• pp.139-144
• /
• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• 조명전기설비학회논문지
• /
• 제25권12호
• /
• pp.48-53
• /
• 2011

Polymer thin films were prepared by capacitively coupled plasma polymerization process for application of gate insulator. The polymer thin films revealed to form polymer layers with original properties of the monomer. Among the plasma polymer thin films, the styrene polymer having large number of phenyl sites revealed higher dielectric constant of k=3.7 than that of conventional polymer. The plasma polymerized styrene thin film revealed no hysteresis characteristics and low leakage current density of $1{\times}10^{-8}[Acm^{-2}]$ at field strength of $1[MVcm^{-1}]$, which measured by I-V and C-V measurements using MIM and MIS devices.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1993년도 하계학술대회 논문집 B
• /
• pp.1292-1294
• /
• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

• 한국표면공학회지
• /
• 제41권1호
• /
• pp.1-5
• /
• 2008

In this work, improvement of mechanical and electrical properties of gate dielectric layer for flexible organic thin film transistor (OTFT) devices was investigated. In order to increase the mechanical flexibility of PVP (poly(4-vinyl phenol) organic gate dielectric, a very thin inorganic $HfO_2$ layers with the thickness of $5{\sim}20nm$ was inserted in between the spin-coated PVP layers. Insertion of the inorganic $HfO_2$ in the laminated organic/inorganic structure of PVP/$HfO_2$/PVP layer led to a dramatic reduction in the leakage current compared to the pure PVP layer. Under repetitive cyclic bending, the leakage current density of the laminated PVP/$HfO_2$/PVP layer with the thickness of 20-nm $HfO_2$ layer was not changed, while that of the single PVP layer was increased significantly. Mechanical flexibility tests of the OTFT devices by cyclic bending with 5 mm bending radius indicated that the leakage current of the laminated PVP/$HfO_2$(20 nm)/PVP gate dielectric in the device structure was also much smaller than that of the single PVP layer.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제10권3호
• /
• pp.240-250
• /
• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• 한국진공학회지
• /
• 제18권2호
• /
• pp.147-150
• /
• 2009

Polydimethylsiloxane (PDMS) 기능성 박막을 도입하여 적은 게이트 누설 전류 특성을 가지는 유기트랜지스터를 제작하고 평가하였다. UV/ozone 처리를 하여 PDMS 표면에 위치한 소수성의 메틸 그룹의 화학적 결합을 끊어 친수성 실리콘 산화막 성질로 표면을 변화시키고 선택적인 펜타신 증착을 유도하였다. Off 전압상태 ($V_g-V_t>0$)에서 게이트 전압에 의해 기인하는 누설 전류는 선형영역 ($V_d=-5\;V$)과 포화영역 ($V_d=-30\;V$)에서 ${\sim}10^{-10}$ A의 값을 보여주며 기존의 트랜지스터 보다 개선된 누설 전류 특성을 나타내었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 학술대회지
• /
• pp.460-462
• /
• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• Korean Chemical Engineering Research
• /
• 제48권6호
• /
• pp.737-740
• /
• 2010

높은 누설 전류와 문턱 전압의 이동은 비정질 실리콘(a-Si:H) 트랜지스터(TFT)의 단점이다. 이러한 특성은 게이트 절연체와 활성층 박막의 막 특성, 표면 거칠기와 공정 조건에 따라 영향을 받는다. 본 연구의 목적은 누설 전류와 문턱 전압의 특성을 개선하는데 목적이 있다. 게이트 절연체의 공정 조건에 대해서는 질소를 증가한 증착 공정 조건을 적용하였고, 활성층의 공정 조건에 대해서는 산소를 증가한 공정 조건을 적용하여 전자 포획을 감소시키고 박막의 밀도를 증가시켰다. $I_{off}$는 $65^{\circ}C$ 조건하에서 1.01 pA에서 0.18pA로, ${\Delta}V_{th}$는 -1.89 V에서 -1.22V로 개선되었다.