• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• 대한전자공학회논문지SD
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• 제47권10호
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• pp.1-6
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• 2010

본 연구에서는 S-파라미터 측정 데이터를 사용하는 RF측정방법으로 short-channel MOSFET의 RF 캐패시턴스 전압(C-V) 곡선을 상온에서 $225^{\circ}C$까지 추출하였으며, 추출된 고온 종속 특성을 엠피리컬하게 모델링하였다. RF C-V 특성곡선의 weak inversion영역에서 온도 변화에 따른 voltage shift가 threshold voltage shift보다 적은 현상이 관찰되었지만, 기존 long-channel C-V 이론 방정식으로 설명할 수 없는 현상임이 입증되었다. 이러한 short-channel C-V 곡선의 고온 종속 모델링을 위해서 새로운 엠피리컬 방정식이 개발되었다. 이 방정식의 정확도는 모델된 C-V곡선과 측정 데이터가 넓은 온도범위에서 잘 일치하는 결과를 관찰함으로써 입증되었다. 또한, 높은 게이트 전압에서는 온도가 증가함에 따라 채널 캐패시턴스 값이 감소하는 것을 확인할 수 있다.

• 대한전자공학회논문지SD
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• 제37권12호
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• pp.1-9
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• 2000

미세구조 N-채널 MOSFET의 게이트-소스 전압에 의존하는 유효 채널 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출을 위해서 새로운 ERM-방법을 제안하였다. ERM-방법은 선형영역에서 동작하는 게이트 길이가 다른 두개의 소자($W_m/L_m=30{\mu}m/0.6{\mu}m, 30{\mu}m/1{mu}m$)에 적용되었고 유효 채널 캐리어 이동도를 모델링하고 추출하는 과정에서 게이트-소스 전압에 의존하는 소스 및 드레인 기생저항의 영향을 고려하였다. ERM-방법으로 추출된 특성변수들을 사용한 해석적 모델식과 소자의 측정데이터를 비교해본 결과 오차가 거의 없이 일치하는 것을 확인하였다. 따라서, ERM-방법을 사용하면 대칭구조 및 비대칭구조 소자의 유효 채널 캐리어 이동도, 소스 및 드레인 기생저항과 다른 특성변수들을 정확하고 효율적으로 추출할 수 있을 것으로 기대된다.

• 전자공학회논문지A
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• 제31A권4호
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• pp.77-83
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• 1994

In this paper we numerically approximated the field-effect mobility of a-Si:H TFT. Field-effect mobility, based on the charge-trapping model and new effective capacitance model in our study, used Chebyshev approximation was approximated as the function of gate potential(gate-to-channel voltage). Even though various external factors are changed, this formula can be applied by choosing the characteristic coefficients without any change of the approximation formula corresponding to each operation region. Using new approximated field-effect mobility formula, the dependences of field-effect mobility on materials and thickness of gate insulator, thickness of a-Si bulk, and operation temperature in inverted staggered-electrode a-Si:H TFT were estimated. By this was the usefulness of new approximated mobility formula proved.

• 센서학회지
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• 제30권6호
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.491-491
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• 2011

Transparent and flexible electronic devices that are light-weight, unbreakable, low power consumption, optically transparent, and mechanical flexible possibly have great potential in new applications of digital gadgets. Potential applications include transparent displays, heads-up display, sensor, and artificial skin. Recent reports on transparent and flexible field-effect transistors (tf-FETs) have focused on improving mechanical properties, optical transmittance, and performances. Most of tf-FET devices were fabricated with transparent oxide semiconductors which mechanical flexibility is limited. And, there have been no reports of transparent and flexible all-organic tf-FETs fabricated with organic semiconductor channel, gate dielectric, gate electrode, source/drain electrode, and encapsulation for sensor applications. We present the first demonstration of transparent, flexible all-organic sensor based on multifunctional organic FETs with organic semiconductor channel, gate dielectric, and electrodes having a capability of sensing infrared (IR) radiation and mechanical strain. The key component of our device design is to integrate the poly(vinylidene fluoride-triflouroethylene) (P(VDF-TrFE) co-polymer directly into transparent and flexible OFETs as a multi-functional dielectric layer, which has both piezoelectric and pyroelectric properties. The P(VDF-TrFE) co-polumer gate dielectric has a high sensitivity to the wavelength regime over 800 nm. In particular, wavelength variations of P(VDF-TrFE) molecules coincide with wavelength range of IR radiation from human body (7000 nm ~14000 nm) so that the devices are highly sensitive with IR radiation of human body. Devices were examined by measuring IR light response at different powers. After that, we continued to measure IR response under various bending radius. AC (alternating current) gate biasing method was used to separate the response of direct pyroelectric gate dielectric and other electrical parameters such as mobility, capacitance, and contact resistance. Experiment results demonstrate that the tf-OTFT with high sensitivity to IR radiation can be applied for IR sensors.

• Journal of electromagnetic engineering and science
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• 제14권2호
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• pp.68-73
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• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1564-1567
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• 2008

We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.

• 대한전자공학회논문지
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• 제26권6호
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• pp.38-47
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• 1989

헴트(HEMT) 소자의 순수 해석적 DC모델이 2차원 전하제어 시뮬레이션 결과[4]에 기초하여 제작되었다. 이 모델에서는 2-DEG 채널의 전자 운송 역학에 확산 효과를 추가하였다. 이 확산효과는 기존 1차원 DC모델에서 사용하는 전자 이동도 및 문턱전압을 증가시키는 효과를 가졌음을 보였다. 또한 2-DEG 농도분포함수를 piecewise 선형화하여 HEMT 소자의 subthreshold 특성의 해석적 모델을 추가하였고, 따라서 2-DEG의 채널 두께 및 게이트 용량을 게이트 전압의 함수로 나타내었다. I-V curve의 전류포화영역에서의 기울기를 모델하는데는 gate 밑의 전자포화채널 지역에서의 전자채널두께와 채널길이 변조현상을 함께 고려하였다. Troffimenkoff형의 전장의존 전자이동도를 사용하여 I-V곡선의 포화현상을 모델하였다. 또한 기존 1차원 모델에서 감안되지 않은 2차원 효과가 실제 전류특성곡선에서 매우 중요한 역할을 하며, 이 효과가 효과적으로 1개의 보정상수f로 보상됨을 보였고, 물리적으로 이 상수가 채널 GCA 지역과 채널포화지역 사이에 형성되는 채널천이지역의 전자농도와 관계됨을 보였다.