• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.44-48
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• 1999

In order to the investigate for the DC(forward-reverse) breakdown properties of gate oxide in MOSFET, we are manufactured the specimen as following. The resistivity is 1.2($\Omega$ $.$ cm), 1.5($\Omega$ $.$ cm) and 1.8($\Omega$ $.$ cm) when thickness is 600(${\AA}$), and the diffusion time is both 110[min] and 150[min] when thickness is 600[${\AA}$]. In DC dielectric strength due to the each resistivity, it is confirmed that almost of the leakage current and breakdown current is flowed through n+ source when positive bias is applied, but is flowed through P region when negative bias is applied. It is thought that the dielectric strength due to the diffusion time is the contribution as increasing of p region.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.583-586
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• 2011

In this paper, subthreshold swing characteristics have been presented for double-gate MOSFETs, using the analytical model based on series form of potential distribution. Subthreshold swing is very important factor for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec. The channel length $L_g$ is varied from 30nm to 100nm, and channel thickness $t_{si}$ from 15 to 20nm according to channel length, and oxide thickness 5nm to investigate subthreshold swing. The doping of channel is fixed with $10^{16}cm^{-3}$ p-type. The results show good agreement with numerical simulations, confirming this model.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.651-656
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• 2014

This paper analyzed the change of subthreshold swing for channel doping of asymmetric double gate(DG) MOSFET. The subthreshold swing is the factor to describe the decreasing rate of off current in the subthreshold region, and plays a very important role in application of digital circuits. Poisson's equation was used to analyze the subthreshold swing for asymmetric DGMOSFET. Asymmetric DGMOSFET could be fabricated with the different top and bottom gate oxide thickness and bias voltage unlike symmetric DGMOSFET. It is investigated in this paper how the doping in channel, gate oxide thickness and gate bias voltages for asymmetric DGMOSFET influenced on subthreshold swing. Gaussian function had been used as doping distribution in solving the Poisson's equation, and the change of subthreshold swing was observed for projected range and standard projected deviation used as parameters of Gaussian distribution. Resultly, the subthreshold swing was greatly changed for doping concentration and profiles, and gate oxide thickness and bias voltage had a big impact on subthreshold swing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1648-1653
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• 2006

In this paper, transport characteristics have been investigated using analytical current-voltage model for double gate MOSFET(DGMOSFET). Scaling down to 100nm of gate length for MOSFET can bring about various problems such as a threshold voltage roll-off and increasing off current by tunneling since thickness of oxide is down by 1.fnm and doping concentration is increased. A current-voltage characteristics have been calculated according to changing of channel length,using analytical current-voltage relation. The analytical model has been verified by calculating I-V relation according to changing of oxide thickness and channel thickness as well as channel length. A current-voltage characteristics also have been compared and analyzed for operating temperature. When gate voltage is 2V, it is shown that a current-voltage characteristic in 77K is superior to in room temperature.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.91-95
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• 1990

We study the process for the reduction of bird's beak at LOCOS processing with changing the representative coefficients, oxide thickness, silicon nitride thickness, oxidetion temperature and field oxide thickness that induced the condition of bird'beak. In order to eliminate the gate oxide defects induced by selective oxidation, we used additional sacrific oxidatio. Finally we obtained the length of bird's beak to be 5000\ulcornerby SEM.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1422-1424
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• 2009

Modified self-assembled $TiO_2$ and polyelectrolyte multilayer film have been used as OTFT insulator. Both films were used as gate insulator and their thickness were reduced to the order of 10nm. The operating voltage of OTFT was substantially reduced due to nanoscale thickness of titanium oxide and polyelectrolyte multilayer. Pentacene-based OTFT characteristics will be discussed.

• Proceedings of the IEEK Conference
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• summer
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation