• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.73-76
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• 2020

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

• ETRI Journal
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• v.31 no.6
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• pp.725-731
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• 2009

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.601-608
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• 2014

In this paper, we have characterized the electrical properties related to gate leakage current in AlGaN/GaN MISHFETs with varying the thickness (0 to 10 nm) of $Al_2O_3$ gate insulator which also serves as a surface protection layer during high-temperature RTP. The sheet resistance of the unprotected TLM pattern after RTP was rapidly increased to $1323{\Omega}/{\square}$ from the value of $400{\Omega}/{\square}$ of the as-grown sample due to thermal damage during high temperature RTP. On the other hand, the sheet resistances of the TLM pattern protected with thin $Al_2O_3$ layer (when its thickness is larger than 5 nm) were slightly decreased after high-temperature RTP since the deposited $Al_2O_3$ layer effectively neutralizes the acceptor-like states on the surface of AlGaN layer which in turn increases the 2DEG density. AlGaN/GaN MISHFET with 8 nm-thick $Al_2O_3$ gate insulator exhibited extremely low gate leakage current of $10^{-9}A/mm$, which led to superior device performances such as a very low subthreshold swing (SS) of 80 mV/dec and high $I_{on}/I_{off}$ ratio of ${\sim}10^{10}$. The PF emission and FN tunneling models were used to characterize the gate leakage currents of the devices. The device with 5 nm-thick $Al_2O_3$ layer exhibited both PF emission and FN tunneling at relatively lower gate voltages compared to that with 8 nm-thick $Al_2O_3$ layer due to thinner $Al_2O_3$ layer, as expected. The device with 10 nm-thick $Al_2O_3$ layer, however, showed very high gate leakage current of $5.5{\times}10^{-4}A/mm$ due to poly-crystallization of the $Al_2O_3$ layer during the high-temperature RTP, which led to very poor performances.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.42-42
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• 2009

To make up for the disadvantages of PVA gate, we blend PVP(20% wt) with PVA(5% wt) as a gate material. The best ratio for the mixture was 5:5, PVP-PVA blended gate used MIM structure showed better performance in leakage current and capacitance. PVP-PVA blended gate was fabricated by spin-coating process and pentacene was used as an organic TFT channel layer by thermal evaporation. Overall OTFT performance has also increased as PVP-PVA blended gate has relatively lower leakage current and higher capacitance than pure PVA gate has.

• Korean Journal of Materials Research
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• v.13 no.1
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• pp.11-17
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• 2003

DC characteristics of recessed gate 4H-SiC MESFET were investigated using the device/circuit simulation tool, PISCES. Results of theoretical calculation were compared with the experimental data for the extraction of modeling parameters which were implemented for the prediction of DC and gate leakage characteristics at high temperatures. The current-voltage analysis using a fixed mobility model revealed that the short channel effect is influenced by the defects in SiC. The incomplete ionization models are found out significant physical models for an accurate prediction of SiC device performance. Gate leakage is shown to increase with the device operation temperatures and to decrease with the Schottky barrier height of gate metal.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.171-175
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• 1996

Gate insulator for Si field emitter is usually formed by e-beam evaporation. However, the evaported oxide requires densification for a stable process and a reduction of gate leakage which results from its Si-rich and nonstoicheiometric structure. In this study, we have developed the process technology able to densify the evaporated oxide in H$_{2}$O ambient. Using this process, we have fabricted thefield emitter array with 625 emitters per pixel, of which gate hole diameter is 1.4.mu.m, for the pixel, anode current of 14.3.mu.A was extracted at a gate bias of 100V and gate leakage was about 0.27% of the total emission current.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.