Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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gate stack구조를 이용한 LTPS TFT의 전기적 특성 분석

  • 전병기 (성균관대학교 전자전기공학과) ;
  • 조재현 (성균관대학교 전자전기공학과) ;
  • 이준신 (성균관대학교 전자전기공학과)
  • Published : 2009.11.12
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Abstract

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

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