• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.822-824
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• 2007

This paper investigated a gate driver circuit with amorphous silicon for mobile TFT-LCD. In the conventional circuit, the fluctuation of the off-state voltage causes the fluctuation of gate line voltages in the panel and then image quality becomes worse. Newly designed gate driver circuit with dynamic switching inverter and carry out signal reduce the fluctuation of the off-state voltage because dynamic switching inverter is holding the off-state voltage and the delay of carry signal is reduced. The simulation results show that the proposed a-Si:H gate driver has low noise and high stability compared with the conventional one.

• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• 전력전자학회논문지
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• 제4권2호
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• pp.111-121
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• 1999

대용량 IGBT를 위한 새로운 능동 게이트 구동회로를 제안한다. IGBT의 우수한 스위칭 성능을 성취하기 위해 필요한 여러 구동 조건들을 최적으로 조합시킨 게이트 구동 회로이다. 스위칭 노이즈와 스트레스를 감소시키기 위해 필요한 느린 구동 조건과 스위칭 속도를 증가시키고 손실을 저감시키기 위해 요구되는 고속 구동 조건들을 동시에 만족시키고 있다. 또한 작은 전류의 턴-온시 발생되는 진동현상을 효과적으로 감쇠시킬 수 있는 특성을 지니고 있다.

• 대한전자공학회논문지
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• 제14권3호
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• pp.6-11
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• 1977

GaAs Schottky Barrier Gate 전계효과트랜지스터의 잡음동작을 잡음등가회로를 사용하여 연구하였으며, 부가구인 잡음근원은 pinch-off영역에서 GaAs FET bias에 의하여 구현되었다. 이것이 바로 intervalley 산란잡음과 hot electron에 의한 잡음이었다. 본 논문의 잡음등가회로에서는 carrier의 포화속도와 기생저항의 영향을 고려한 parameter를 정하였다.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.73-76
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• 2020

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• 전자공학회논문지 IE
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• 제47권1호
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• pp.1-5
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• 2010

본 논문은 SOI 저장음 종폭기에서 게이트구조가 핫캐리어에 의한 성능저하에 미치는 영향융 조사하였다. 회로 시뮬레이션은 H-게이트와 T-게이트를 가지는 SOI MOSFET에서 측정된 S-파라미터와 Agilent사의 ADS를 사용하여 스트레스 전후의 H-게이트와 T-게이트 저잡음 증폭기의 성능을 비교하였다. 또한 저잡음 증폭기의 장치 열화와 성능 열화 사이의 관계뿐만 아니라 임피던스 매칭(S11), 잡음 지수와 이득에 관한 저잡음 증폭기의 성능 지수 등을 논의하였다.

• 한국통신학회논문지
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• 제17권5호
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• pp.509-520
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• 1992

AIGaAs/GaAs HBT를 이용한 고속 디지틀 시스템에 사용 될 CML OR/NOR 논리게이트를 설계하였다. HBT모델링은 직접 추출법, Gummel-poon모델을 혼합한 형태로 등가회로를 얻었으며 PSPICE를 이용한 시뮬레이션 결과, 전달지연시간이 25ps로써 차단 토글주파수가200Hz에 이르는 초고속 특성을 가지고 기 보고된 HBT의 ECL이나 ME.IFET SCFL에 비하여 noise margin이 커서 입력변동에 비한 잡음에 강하며 fan-out특성이 우수함을 확인하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.542-545
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• 2002

This paper deals with the optimization inverter design and minimization Conduced EMI noise by customizing IPM(Intelligent Power Module). Generally, In case of IPM, we realized that the trade-off relation between switching loss and spike voltage. Higher gate resistor causes tile lower spike voltage and the higher turn-off switching loss. But we know that the life cycle of inverter and the susceptibility of noise, so we optimized the gate resistor. Proposed method is that optimized the gate resistor suitable for the inverter and motor. The simulation and experimental results show that the spike voltage and Conduced EMI noise can be reduced without the additional circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.650-656
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• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.