• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.2
• /
• pp.72-77
• /
• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.5
• /
• pp.879-886
• /
• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.122-130
• /
• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.7 s.110
• /
• pp.638-647
• /
• 2006

Recently, the DFT-Spread OFDM has been studied for the PAPR reduction. However, the DFT-Spread OFDM produces more ICI and SCI problems than OFDM because phase offset mismatch of the DFT spreading code results from the random phase noise in the oscillator. In this paper, at first, phase noise influence on the DFT-Spread OFDM system is theoretically analyzed in terms of the BER performance. Then, the conventional ICI self-cancellation methods are discussed and two kinds of ICI self-cancellation methods are newly proposed. Lastly, a new DFT-Spread OFDM system which selectively adopts the ICI self-cancellation technique is proposed to resolve the interference problem and PAPR reduction simultaneously. Proposednew DFT-Spread OFDM system can minimize performance degradation caused by phase noise, and still maintain the low PAPR property. Among the studied methods, DFT-Spread OFDM with data-conjugate method or newly proposed symmetric data-conjugate method show the significant performance improvements, compared with the DFT-Spread OFDM without ICI self-cancellation schemes. The data-conjugate method is slightly better than symmetric data-conjugate method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.5
• /
• pp.519-527
• /
• 2010

In this paper, we proposed a 13.56 MHz wireless power transfer system using loop antennas with tunable impedance matching circuits. In general, a wireless power transfer system shows an impedance mismatching due to a reflected impedance, because a coupling coefficient is varied with respect to separation distance between two resonating antennas. The proposed system can compensate the effect of this impedance mismatch owing to tunable impedance matching circuits using varactor diodes. Therefore, transmission efficiency is enhanced, moreover, the center frequency of the system is not changed, regardless of separation distance between two antennas. In order to demonstrate the performance of the proposed system, a wireless power transfer system with tunable impedance matching circuits is designed and implemented, which has a pair of loop antennas with a dimension of $30\;cm{\times}30\;cm$ cm. The input return loss, coupling coefficient, efficiency, and input impedance variation with respect to a distance between loop antennas were measured. From measured results, the proposed system shows enhanced performances than the case of the general fixed $50\;{\Omega}$ impedance matching circuits. Therefore, we verified that the proposed wireless power transfer system using the proposed impedance matching scheme will be able to ensure robust operation even when the separation distance of antennas is varied.

• Culinary science and hospitality research
• /
• v.20 no.6
• /
• pp.13-27
• /
• 2014

This study sought to examine the effects of job inconsistency of cooks in the food service businesses on job performance, and the effects of such causation on intention of changing jobs. For job inconsistency, cooks produce limited menu products due to the segmentation of jobs in the same industry, and can hardly exercise their skills obtained through education. Thus, 275 samples of job inconsistency were made to undergo frequency analysis, factor analysis, reliability analysis, correlational analysis, and multiple regression analysis, using the SPSS 17.0 program. Hypothesis 1 was established as cooks' job inconsistency having a positive effect on job performance; thus, with regard to job performance factors, skill inconsistency (${\beta}$=-.432), and wage inconsistency (${\beta}$=-.250) had a negative effect on job performance, but education inconsistency (${\beta}$=-.048) did not have an effect. Hypothesis 2 was established as cooks' job performance having a significant effect on intention of changing jobs; thus, intention of changing jobs had a significant negative effect on job performance (${\beta}$=-.238). So if job performance was improved, the intention of changing jobs would be reduced. This study implies that: cooks who were engaging in the food service businesses experienced job inconsistency, and led themselves to having an intention to change jobs; in this process, individual cooks' job level inconsistency and their wage levels have an important effect on intention of changing jobs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.1-8
• /
• 2005

An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1999.07a
• /
• pp.122-122
• /
• 1999

Graphite with its advantages of high thermal conductivity, low thermal expansion coefficient, and low elasticity, has been widely used as a structural material for high temperature. However, graphite can easily react with oxygen at even low temperature as 40$0^{\circ}C$, resulting in CO2 formation. In order to apply the graphite to high temperature structural material, therefore, it is necessary to improve its oxidation resistive property. Silicon Carbide (SiC) is a semiconductor material for high-temperature, radiation-resistant, and high power/high frequency electronic devices due to its excellent properties. Conventional chemical vapor deposited SiC films has also been widely used as a coating materials for structural applications because of its outstanding properties such as high thermal conductivity, high microhardness, good chemical resistant for oxidation. Therefore, SiC with similar thermal expansion coefficient as graphite is recently considered to be a g행 candidate material for protective coating operating at high temperature, corrosive, and high-wear environments. Due to large lattice mismatch (~50%), however, it was very difficult to grow thick SiC layer on graphite surface. In theis study, we have deposited thick SiC thin films on graphite substrates at temperature range of 700-85$0^{\circ}C$ using single molecular precursors by both thermal MOCVD and PEMOCVD methods for oxidation protection wear and tribological coating . Two organosilicon compounds such as diethylmethylsilane (EDMS), (Et)2SiH(CH3), and hexamethyldisilane (HMDS),(CH3)Si-Si(CH3)3, were utilized as single source precursors, and hydrogen and Ar were used as a bubbler and carrier gas. Polycrystalline cubic SiC protective layers in [110] direction were successfully grown on graphite substrates at temperature as low as 80$0^{\circ}C$ from HMDS by PEMOCVD. In the case of thermal MOCVD, on the other hand, only amorphous SiC layers were obtained with either HMDS or DMS at 85$0^{\circ}C$. We compared the difference of crystal quality and physical properties of the PEMOCVD was highly effective process in improving the characteristics of the a SiC protective layers grown by thermal MOCVD and PEMOCVD method and confirmed that PEMOCVD was highly effective process in improving the characteristics of the SiC layer properties compared to those grown by thermal MOCVD. The as-grown samples were characterized in situ with OES and RGA and ex situ with XRD, XPS, and SEM. The mechanical and oxidation-resistant properties have been checked. The optimum SiC film was obtained at 85$0^{\circ}C$ and RF power of 200W. The maximum deposition rate and microhardness are 2$mu extrm{m}$/h and 4,336kg/mm2 Hv, respectively. The hardness was strongly influenced with the stoichiometry of SiC protective layers.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.5 s.347
• /
• pp.54-63
• /
• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.77-85
• /
• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.