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An Area-Efficient DC-DC Converter with Poly-Si TFT for System-On-Glass  

Lee Kyun-Lyeol (Div. Electrical and Computer Eng., Hanyang Univ.)
Kim Dae-June (Div. Electrical and Computer Eng., Hanyang Univ.)
Yoo Changsik (Div. Electrical and Computer Eng., Hanyang Univ.)
Publication Information
Abstract
An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.
Keywords
DC-DC 변환회로;전하 펌핑 회로;다중 위상 클럭;
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Times Cited By KSCI : 2  (Citation Analysis)
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1 R. Jacob Baker, Harry W. Li, and David E. Boyce, 'CMOS Circuit Design, Layout, and Simulation', IEEE Press, pp. 685-703, 1998
2 M. Bazes, 'Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers', IEEE Journal of solid-state Circuits, Vol. 26, No. 2, pp. 165-168, February 1991   DOI   ScienceOn
3 Pierre Favrat, et al., 'A High-Efficiency CMOS Voltage Doubler', IEEE Journal of Solid-State circuits, VOL. 33, No. 3, March 1998   DOI   ScienceOn
4 Toru Tanzawa and Shigeru Atsumi, 'Optimization of Word-Line Booster Circuits for Low-Voltage Flash Memories', IEEE Journal of Solid-State Circuits, VOL. 34, No. 8. August 1999   DOI   ScienceOn
5 유창식, 김대준, 이균렬, 'System-on-Glass를 위한 poly-Si TFT 아날로그 회로', 한국정보디스플레이학회지, 제 5권, 제 1호, 2004년 2월
6 John F. Dickson, 'On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique', IEEE Journal of solid-state circuits, VOL. SC-11, NO. 3, June 1976   DOI