• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1613-1616
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• 2008

A Transcutaneous Energy Transmission System (TET) has been developed for the wireless energy transmission with two magnetically coupled coils. A resonance circuit is used to raise the induced voltage and current of the secondary coil. Its resonance frequency depends on the internal resistance of circuit and the transferred energy. Because the transferred energy usually changes in wide range, the output voltage is unstable and the energy transferring efficiency decrease. A push-pull class E amplifier is usedto generate high frequency AC voltage. To maintain proper resonance frequency, the voltage output of the amplifier was continuously monitored and adjusted to the optimized resonance frequency. Because of its high frequency (370 kHz), a phase lockedloop circuit and a comparator are used to monitor the output waveform. The results of experimentaldata show that the PLL circuit can increase the transmission efficiency and stabilize the output voltage of TET.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• ETRI Journal
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• 제21권3호
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• pp.1-5
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• 1999

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• ETRI Journal
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• 제30권2호
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.224-228
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• 2003

In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

• 한국정보통신학회논문지
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• 제11권5호
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• pp.949-954
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• 2007

본 논문에서는 CMOS 공정을 이용하여 동작온도에 무관한 FVC(Frequency-to-Voltage Convener) 회로를 제안한다. FVC는 FLL(Frequency Locked Loop)의 핵심 회로로서 주파수 신호를 전압신호로 변환하는 회로이다. FLL 회로는 PLL(Phase-Locked Loop) 회로 같이 고정된 주파수 신호를 생성하는 회로지만, PLL과는 달리 위상비교기, charge pump, 저역 필터 등이 필요치 않아 간단히 회로를 구성할 수 있다. FVC 회로의 설계는 $0.25{\mu}m$ CMOS 공정을 이용하였다. 설계되어진 회로의 입력 주파수는 70MHz에서 140MHz를 사용하였다. 회로의 시뮬레이션 결과 동작 온도가 $0^{\circ}C$에서 $75^{\circ}C$까지 변화할 때 변환된 출력 전압의 변화는 상온에 비하여 ${\pm}2%$이내였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.95-99
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• 2000

New locking algorithm of DLL is proposed to improve the locking speed and low power dissipation in this paper, In spite of using the architecture of delay controller, low power consumption is acquired by operating only one controller at once and fast locking speed is accomplished by initial setting from the coarse controller. The proposed DLL circuit is operated from 50MHz to 200MHz and locked within 6 cycle at all of operating frequency.