Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design of DLL(Delay-Locked-Loop) using new Locking Algorithm

새로운 Locking 알고리즘을 이용한 DLL(Delay-Locked-Loop) 설계

  • 경영자 (청주대학교 전자공학과) ;
  • 김태엽 (청주대학교 전자공학과) ;
  • 이광희 (청주대학교 전자공학과) ;
  • 손상희 (청주대학교 전자·정보통신·반도체공학부)
  • Published : 2000.11.01
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Abstract

New locking algorithm of DLL is proposed to improve the locking speed and low power dissipation in this paper, In spite of using the architecture of delay controller, low power consumption is acquired by operating only one controller at once and fast locking speed is accomplished by initial setting from the coarse controller. The proposed DLL circuit is operated from 50MHz to 200MHz and locked within 6 cycle at all of operating frequency.

Keywords