• Title/Summary/Keyword: folder 회로

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Circuit design of current driving A/D converter (전류 구동형 A/D converter 회로 설계)

  • Lee, Jong-Gyu;Oh, Woo-Jin;Kim, Myung-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.11
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    • pp.2100-2106
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    • 2007
  • Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

A Convergent Synthesis of (Z)-13-Octadecen-1-yl Acetate, the Pheromone Mimic of the Rice Leaf Folder Moth and Its Biological Activity Test

  • Kang Suk-Ku;Moon Byoung-Ho;Lee Jeang-Oon;Goh Hyun-Gwan
    • Bulletin of the Korean Chemical Society
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    • v.6 no.4
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    • pp.228-230
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    • 1985
  • (Z)-13-Octadecen-1-yl acetate, the pheromone mimic of the Rice Leaf Folder Moth, Cnaphalocrosis medinalis, was synthesized from 1,13-tridecanediol in three steps. Monoacetylation of 1,13-tridecanediol followed by PCC oxidation gave 13-acetoxytridecan-1-al. Wittig olefination of the 13-acetoxytridecan-1-al with pentylidenetriphenylphosphonium ylide afforded (Z)-13-octadecen-1-yl acetate, the pheromone mimic of the Rice Leaf Folder.

Automatic Layout of High Density PLA (고밀도 PLA의 자동 Layout System의 구성)

  • 이제현;경종민
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.22 no.6
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    • pp.13-18
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    • 1985
  • A set of utility programs for automatic generation, minimization and verification of high density PLA layout was developed, which includes equation-to-truth table translator, logic minimizer, PLA product term sorter, file generator for plotting stick diagram, dynamic CMOS PLA layout generator and bipartite row folded CMOS PLA layout generator. Size reduction is performed mainly by logic minimizer and bipartite row folder, and the maximal delay is reduced by sorter. The fOe for automatically generated layout is stored in CIF. Each program was written in Clanguage, and was run on VAX-11/750 (UNIX).

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Comparison of Growth, Yield and Quality between Organic Cultivation and Conventional Cultivation in Rice (Oryza sativa L.) Field (벼 유기재배와 관행재배의 생육 및 수량과 품질 비교)

  • Cha, Kwang-Hong;Oh, Hwan-Jung;Park, Ro-Dong;Park, Heung-Gyu;An, Kyu-Nam;Jung, Woo-Jin
    • Korean Journal of Organic Agriculture
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    • v.18 no.2
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    • pp.199-208
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    • 2010
  • To investigate a comparison of rice yield and quality between organic and conventional cultivation, study for occurrence of rice diseases carried out in rice (Oryza sativa L.) field of Noahn and Bannam region. The results obtained as following: 1) Bactericide and insecticide were applied twice and four times at Noahn and Bannam region in conventional cultivation (C.C) of rice field, respectively, it was applied twice at two region in organic cultivation (O.C). Rice strip virus, leaf blast, neck blast, sheath blight, bacterial leaf blight, rice water weevil, rice leaf folder, and plant hoppers were occurred mainly in rice field. Leaf blast, neck blast, and rice leaf folder were occurred highly at O.C compared with C.C. 2) Growth level of rice in clum and panicle length was lower at O.C than C.C. Number of panicles per hill was by 0.6 higher at O.C than C.C. Number of panicles per hill was by 0.6 higher at O.C than C.C in Noahn region. Number of spikelets per panicle, grain filling ratio, brown/rough rice ratio, and weight of 1,000 grains was lower at O.C than C.C. Number of panicles per hill was by 0.8 lower at O.C than C.C in Bannam region. Number of spikelets per panicle and grain filling ratio was higher at O.C than C.C while brown/rough rice ratio was lower at O.C. Total yield percentage of rice in O.C was level of 84% at Noahn region and 94% at Bannam region compared with C.C. 3) Head rice percentage was lower at in O.C than C.C at two region. Protein and palatability (Toyo value) were lower at O.C than C.C in Bannam region causing occurrence of neck blast and rice leaf folder by oversupply of nitrogen fertilizer. Protein, whiteness, and palatability (Toyo value) were adequate level at O.C in Noahn region by lower nitrogen fertilizer.

Arm-up holder의 보조기구 제작에 따른 유용성 평가

  • 이현직;최병기;심재구;김종식;오동균;박영환
    • The Journal of Korean Society for Radiation Therapy
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    • v.14 no.1
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    • pp.85-88
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    • 2002
  • I. 목적 : arm-up holder는 흉부 및 복부 질환 치료의 환자고정에 유용하게 사용하고 있으나 손잡이 부분과 어깨가 닿는 부분까지 거리 때문에 동일한 자세를 유지하는데 불편함이 있다. 특히 긴장을 많이 하거나 기력이 없는 환자는 방사선 치료 시 자세의 불안정으로 인하여 치료의 정확성이 떨어질 수 있다. 이에 본원에서는 현재 사용하고 있는 arm-up holder에 팔의 지지를 위한 보조기구를 제작하여 유용성을 평가하였다. II. 대상 및 방법 : 기존의 arm-up holder에 어깨받침대를 부착하여 개선된 arm-up holder를 제작하였다. 실험을 위하여 기존의 arm-up holder를 사용하는 환자그룹과 개선된 arm-up holder를 사용하는 그룹으로 구분하여 자세 변화를 평가하였다. 두 그룹의 환자를 대상으로 모의 치료를 실시한 후 치료실에서 L-gram 을 2회 씩 촬영하여 치료하고자 하는 portal film과 isocenter의 변화를 측정했다. 각 그룹 당 10명씩의 환자를 선정하여 반복 조사하였다. III. 결과 : 개선된 arm-up holder를 사용한 그룹의 isocenter 의 변화는 최대 2mm, 최소 0.5mm 평균 1.2mm 이다. 기존의 arm-up folder를 사용한 그룹과 비교하여 평균변화는 약 2배로 나라났고, 최대 변화는 2.5배의 오차범위가 측정되었다. IV. 결론 : 현재 사용하고 있는 arm-up holder는 흉부 및 복부의 사방향 방사선 치료 시 팔에 의한 방사선 감약을 예방할 수 있는 유용한 고정용구이다. 하지만 팔을 올리고 있는 자세는 환자에게 불편함을 야기 시키며 이로 인한 치료의 정확성을 감소시킬 수 있다. 따라서, 기존의 arm-up holder에 보조기구를 제작하여 사용함으로써 환자의 불편함을 개선하고, set-up 의 안정성과 재현성을 향상시킬 수 있었다.

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Design of an 1.8V 6-bit 1GS/s 60mW CMOS A/D Converter Using Folding-Interpolation Technique (Folding-Interpolation 기법을 이용한 1.8V 6-bit 1GS/s 60mW 0.27$mm^2$ CMOS A/D 변환기의 설계)

  • Jung, Min-Ho;Moon, Jun-Ho;Hwang, Sang-Hoon;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.74-81
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    • 2007
  • In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

SAR analysis with variety of the antenna structures on PCS handset (PCS 전화기의 안테나 구조에 따른 SAR 분석)

  • Kim, Hyoun-Kyoung;Park, Ju-Deok;Kim, Jin-Seok;Kim, Nam
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.11
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    • pp.8-16
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    • 2000
  • In this paper, on calculating SARs on human head using computer simulation, SARs caused by PCS handsets are calculated and compared, and the design parameters that affect SAR values are analyzed. Is and 10 g peak averaged SARs are calculated as the type of antenna, the location of antenna, and the type of handset are changed and SAR distributions as depth of human head are shown. Among the antennas on flip type handsets, side mounted PIFA has the lowest SARs 1g and 10g peak averaged SARs are 0.686W/kg and 0.353W/kg. The SARs caused by monopole antenna on folder type handset are 1.133W/kg and 0.709W/kg. and are about 30% lower than monopole 1.759W/kg and 0.978W/kg, respectively. SAR distributions as depth of human head of side mounted PIFA and monopole antenna on folder-type handset are more slowly changed than those of top mounted PIFA and monopole antenna on flip-type handset.

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A 250MS/s 8 Bit CMOS folding and Interpolating AD Converter with 2 Stage Architecture (2단 구조를 사용한 250MS/s 8비트 CMOS 폴딩-인터폴레이팅 AD 변환기)

  • 이돈섭;곽계달
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.826-832
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    • 2004
  • A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

Design of an 1.8V 6-bit 100MS/s 5mW CMOS A/D Converter with Low Power Folding-Interpolation Techniques (저 전력 Folding-Interpolation기법을 적용한 1.8V 6-bit 100MS/s 5mW CMOS A/D 변환기의 설계)

  • Moon Jun-Ho;Hwang Sang-Hoon;Song Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.8 s.350
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    • pp.19-26
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    • 2006
  • In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.

Development of a Model to Evaluate RF Exposure Level from Cellular Phone using a Neural Network (신경망을 이용한 휴대전화에 의한 RF 노출 평가 모델의 개발)

  • Kim Soo-Chan;Nam Ki-Chang;Ahn Seon-Hui;Kim Deok-Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.10 s.89
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    • pp.969-976
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    • 2004
  • The wide and growing use of cellular phones has raised the question about the possible health risks associated with radio-frequency electromagnetic fields. It would be helpful for phone users to blow the exposure levels during cellular phone use. But it is very difficult to recognize the amount of exposure, because measuring accurate level of RF is a difficult matter. In this study, we developed a model to estimate the exposure level and the individual risk of exposure by utilizing the available informations that we can get. We used such parameters as usage time a day, total using period, distance between cellular phone and head, slope of cellular phone, hands-free usage, antenna pulled out or not SAR(Specific Absorption Rate) of cellular phone, and flip or folder type. We proposed a model presenting individual risk of RF exposure from level 0 to 10 by using a neural network.