• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.135-144
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• 2008

A bootstrap circuit is widely used for the floating gate power supply of Intelligent power module (IPM). A bootstrap circuit is simple and inexpensive. However, the duty cycle and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. And the value of the bootstrap capacitor should be increased as the switching frequency decreases. A charge pump circuit can be used to overcome the problems. This paper deals with an analysis and design of a charge pump circuit for the floating gate power supply of an IPM. The simulation and experiment are carried out for an induction motor drive system. The results well verifies the validity of the proposed circuit and design method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• Journal of Industrial Technology
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• v.27 no.B
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• pp.15-20
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• 2007

This paper presents the new design method for the gate driver circuit of the floating MOSFET by using the pulse transformer. Each parameters of the proposed circuit are delivered by the numerical calculation method. By considering inner characteristics of MOSFET, the gate driver makes to increase the efficiency of the power conversion and decrease operating heat. Computer simulations and to experimental results for a Buck Converter are presented in order to validate the proposed method.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• Journal of Korea Water Resources Association
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• v.51 no.5
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• pp.405-415
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• 2018

Hydraulic variables such as discharge coefficient, gate opening, and upstream water depth are required to calculate the discharge of vertical lift gate. It is very important for a precise gate design, because it may affect the rest, to predict the behavior of gate opening during operation. In this study, an equation by which gate opening could be predicted with any upstream water depths was derived from the relation between the calculated value from buoyancy theory and measured one from experiment for a floating gate model. Downpull force was the reason for the differences between the calculated and the measured and it was verified using pressure coefficient. Also, the relation of discharge coefficient with gate opening ratios was derived. The derived relations were used for flood routing and it was realized that downpull force effect should be fully taken into account during gate design.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.647-648
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• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.325-327
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• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.342-344
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• 2005

We have simulated a symmetric dual-gate TFT which has triple floating n+ channel to improve the on-current of the dual-gate TFT. We achieved a low hole concentration at the source and channel junction causes the improvement the potential barrier so that we observed the reduction of the kink-effect. In this paper, we observed the reduction of the kink-effect compared with the conventional single-gate TFT and the improvement of the on-current compared with the conventional dual-gate TFT.