The design to the periphery circuit for operaton and characteristic assessment of the Nano Floating Gate Memory

Nano Floating Gate Memory 의 동작 및 특성 평가를 위한 주변회로 설계

  • Park, Kyung-Soo (Dept. of Information and Display Engineering Hanyang University) ;
  • Choi, Jae-Won (Dept. of Electronics and Computer Engineering Hanyang University) ;
  • Kim, Si-Nae (Dept. of Electronics and Computer Engineering Hanyang University) ;
  • Yoon, Han-Sub (Dept. of Electronics and Computer Engineering Hanyang University) ;
  • Kwack, Kae-Dal (Dept. of Electronics and Computer Engineering Hanyang University)
  • 박경수 (한양대학교 정보디스플레이공학과) ;
  • 최재원 (한양대학교 전자통신컴퓨터공학과) ;
  • 김시내 (한양대학교 전자통신컴퓨터공학과) ;
  • 윤한섭 (한양대학교 전자통신컴퓨터공학과) ;
  • 곽계달 (한양대학교 전자통신컴퓨터공학과)
  • Published : 2006.06.21

Abstract

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

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