• Journal of Information Processing Systems
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• 제8권1호
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• pp.133-144
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• 2012

In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

• 대한한의진단학회지
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• 제25권1호
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• pp.1-71
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• 2021

Objectives In order to reinterpret the meaning of Inch-Bar-Cubit used by pulse diagnosis, this study investigates floating pulses of lung and heart in the Inch area, middle pulse of spleen and livers in the Bar area, and deep pulse of kidney and life gate in the Cubit area. However, some suggested that the meaning of Inch-Bar-Cubit should be interpreted in the same way as floating-middle-deep. Methods In this study, the contents of Inch-Bar-Cubit assignment of pulse diagnosis proposed by Dongeuibogam and Medical Scientist were investigated along with the existing investigation of pulse diagnosis, and their interpretation was investigated. Result and conclusion The assignment of books in Pulse diagnosis can be applied by replacing them with floating-middle-deep instead of Inch-Bar-Cubit.

• 대한전자공학회논문지SD
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• 제43권9호
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• pp.53-58
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• 2006

버텍스 쉐이더는 fixed function T&L(Transform and Lighting) 엔진의 유연성을 향상시키고, 이전보다 다양한 3D 그래픽 효과를 표현하기 위하여 설계되었다. 본 논문의 쉐이더는 DirectX 8.1 의 Vertex Shader 1.1 과 OpenGL ARB에 기초하여 설계하였다. 버텍스 쉐이더는 벡터 연산을 위하여 4개의 ALU로 구성된다. 작은 면적의 저전력 설계를 위하여 32비트 부동소수점 데이터 형식을 24비트 데이터 형식으로 대체하였다. 버텍스 쉐이더 코어의 동작 검증을 위하여 Xilinx Virtex2 300M gate 모듈을 사용하였다. 시납시스 합성결과 TSMC 0.13um 공정에서 115MHz의 주파수로 동작가능하고, 12.5M Polygons/sec 의 연산성능을 보였다. 버텍스 쉐이더 코어의 면적은 동일 공정에서 11만 게이트를 차지한다.

• 접착 및 계면
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• 제23권2호
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• pp.53-58
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• 2022

본 연구는 AlO_x유전체 표면에 유기 자립조립 단분자막 (self-assembled monolayer, SAM) 중간층을 도입함으로써 유전체의 표면특성을 제어하고, 최종적으로 유기전하변조트랜지스터 (Organic charge modulated field-effect transistor, OCMFET)의 전기적 특성을 향상시킨 결과를 제시하였다. 유기 중간층을 적용함으로써, OCMFET의 컨트롤 게이트(CG, Control gate)와 플로팅 게이트 (FG, Floating gate) 사이 커패시터 플레이트로 작용하는 산화알루미늄 게이트 유전체의 표면 에너지를 제어하였으며, FET의 가장 중요한 성능변수인 전계효과 이동도(field-effect transistor, μ_FET)를 향상시켰다. 사용된 SAMs은 네가지의 PA (Octadecylphosphonic acid, Butylphosphonic acid, (3-Bromopropyl)phosphonic acid, (3-Aminopropyl) phosphonic acid)를 사용하여 형성하였으며, 각각 0.73, 0.41, 0.34, 0.15 cm2V^-1s^-1의 μ_OCMFET를 나타내었다. 이 연구를 통해 유기 SAM 중간층의 알킬 체인(Alkyl chain)의 길이 및 말단기의 특성이 소자의 전기적 성능을 제어하는데 중요한 요인임을 확인하였으며, 이 결과를 통해 향후 최적의 센서 플랫폼으로서의 OCMFET 소자성능 최적화에 기여할 수 있을 것으로 기대한다.

• 한국전기전자재료학회논문지
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• 제19권7호
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• 대한전자공학회논문지
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• 제20권2호
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• pp.1-6
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• 1983

MOS 트랜지스터의 채널이 짧아짐에 따라 threshold 전압과 punchthrough 전압이 감소하는 현상을 실리콘 게이트 NMOS 기술로 제작한 소자로써 실험적으로 관찰하였다. 또한 게이트 산화막의 두께를 50nm와 70nm로 감소시키고 보론(boron)을 임플랜트한 소자를 제작하여 게이트 산화막의 두께와 서브스트레이트의 불순물의 농도가 threshold 전압과 Punchthrough 전압의 감소에 미치는 영향을 측정하였다. 또 채널의 길이가 3㎛인 소자에 대하여 hot-electron의 방출을 플로우팅 게이트 패준 방법에 의하여 측정하였으며 그 결과 채널의 길이가 3㎛까지는 hot-electron의 방출은 문제가 되진 않음을 관찰하였다.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.325-328
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• 2002

In this paper. we propose a floating resistor with positive and negative resistance operating at lower supply voltages. The circuit uses only two transistors between the supply voltages. which enable to operate it at low supply voltages. Moreover. the circuit uses fewer number of transistors compared to the reported work. The gate terminal is used in this circuit for the current addition/subraction at the terminals of resistor. The characteristic of the proposed circuit is verified using HSPICE for the power supply +/-1.5V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.