Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2001.11c
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- Pages.165-168
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- 2001
Design of a Floating-Point Divider for IEEE 754-1985 Single-Precision Operations
IEEE 754-1985 단정도 부동 소수점 연산용 나눗셈기 설계
- Park, Ann-Soo (School of Electrical and Electronics Eng, Chung-Ang Univ.) ;
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Chung, Tea-Sang
(School of Electrical and Electronics Eng, Chung-Ang Univ.)
- Published : 2001.11.24
Abstract
This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.
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