• 제목/요약/키워드: field effect transistors

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Graphene field-effect transistor for radio-frequency applications : review

  • Moon, Jeong-Sun
    • Carbon letters
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    • 제13권1호
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    • pp.17-22
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    • 2012
  • Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.

The Effects of Work Function of Metal in Graphene Field-effect Transistors

  • Bae, Giyoon;Park, Wanjun
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.382.1-382.1
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    • 2014
  • Graphene field-effect transistors (GFET) is one of candidates for future high speed electronic devices since graphene has unique electronic properties such as high Fermi velocity (vf=10^6 m/s) and carrier mobility ($15,000cm^2/V{\cdot}s$) [1]. Although the contact property between graphene and metals is a crucial element to design high performance electronic devices, it has not been clearly identified. Therefore, we need to understand characteristics of graphene/metal contact in the GFET. Recently, it is theoretically known that graphene on metal can be doped by presence of interface dipole layer induced by charge transfer [2]. It notes that doping type of graphene under metal is determined by difference of work function between graphene and metal. In this study, we present the GFET fabricated by contact metals having high work function (Pt, Ni) for p-doping and low work function (Ta, Cr) for n-doping. The results show that asymmetric conductance depends on work function of metal because the interfacial dipole is locally formed between metal electrodes and graphene. It induces p-n-p or n-p-n junction in the channel of the GFET when gate bias is applied. In addition, we confirm that charge transfer regions are differently affected by gate electric field along gate length.

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나노임프린트 리소그래피 기술을 이용한 그래핀 나노리본 트랜지스터 제조 및 그래핀 전극을 활용한 실리콘 트랜지스터 응용 (Facile Fabrication Process for Graphene Nanoribbon Using Nano-Imprint Lithography(NIL) and Application of Graphene Pattern on Flexible Substrate by Transfer Printing of Silicon Membrane)

  • 엄성운;강석희;홍석원
    • 한국재료학회지
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    • 제26권11호
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    • pp.635-643
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    • 2016
  • Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped $Si/SiO_2$ substrate. Consequently, we observed an enhancement of the performance of the GNR-transistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.

Fabrication of Graphene p-n Junction Field Effect Transistors on Patterned Self-Assembled Monolayers/Substrate

  • Cho, Jumi;Jung, Daesung;Kim, Yooseok;Song, Wooseok;Adhikari, Prashanta Dhoj;An, Ki-Seok;Park, Chong-Yun
    • Applied Science and Convergence Technology
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    • 제24권3호
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    • pp.53-59
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    • 2015
  • The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구 (Study of monolithic 3D integrated-circuit consisting of tunneling field-effect transistors)

  • 유윤섭
    • 한국정보통신학회논문지
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    • 제26권5호
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    • pp.682-687
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    • 2022
  • 터널링 전계효과 트랜지스터(tunneling field-effect transistor; TFET)로 적층된 3차원 적층형 집적회로(monolithic 3D integrated-circuit; M3DIC)에 대한 연구 결과를 소개한다. TFET는 MOSFET(metal-oxide-semiconductor field-effect transistor)와 달리 소스와 드레인이 비대칭 구조이므로 대칭구조인 MOSFET의 레이아웃과 다르게 설계된다. 비대칭 구조로 인해서 다양한 인버터 구조 및 레이아웃이 가능하고, 그 중에서 최소 금속선 레이어를 가지는 단순한 인버터 구조를 제안한다. 비대칭 구조의 TFET를 순차적으로 적층한 논리 게이트인 NAND 게이트, NOR 게이트 등의 M3DIC의 구조와 레이아웃을 제안된 인버터 구조를 바탕으로 제안한다. 소자와 회로 시뮬레이터를 이용해서 제안된 M3D 논리게이트의 전압전달특성 결과를 조사하고 각 논리 게이트의 동작을 검증한다. M3D 논리 게이트 별 셀 면적은 2차원 평면의 논리게이트에 비해서 약 50% 감소된다.

Flexible biosensors based on field-effect transistors and multi-electrode arrays: a review

  • Kim, Ju-Hwan;Park, Je-Won;Han, Dong-Jun;Park, Dong-Wook
    • Journal of Semiconductor Engineering
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    • 제1권3호
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    • pp.88-98
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    • 2020
  • As biosensors are widely used in the medical field, flexible devices compatible with live animals have aroused great interest. Especially, significant research has been carried out to develop implantable or skin-attachable devices for real-time bio-signal sensing. From the device point of view, various biosensor types such as field-effect transistors (FETs) and multi-electrode arrays (MEAs) have been reported as diverse sensing strategies. In particular, the flexible FETs and MEAs allow semiconductor engineering to expand its application, which had been impossible with stiff devices and materials. This review summarizes the state-of-the-art research on flexible FET and MEA biosensors focusing on their materials, structures, sensing targets, and methods.

Optimization and Characterization of Gate Electrode Dependent Flicker Noise in Silicon Nanowire Transistors

  • Anandan, P.;Mohankumar, N.
    • Journal of Electrical Engineering and Technology
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    • 제9권4호
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    • pp.1343-1348
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    • 2014
  • The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, $I_{on}/I_{off}$ and fringing capacitance using TCAD simulations. Molybdenum based gate electrode showed significant improvement in terms of high drive current, Low DIBL and high $I_{on}/I_{off}$. The noise power sepctral density is reduced by characterizing the device at higher frequencies. Silicon Nanowire with Si3N4 spacer decreases the drain current spectral density which interms reduces the fringing fields there by decreasing the flicker noise.

Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)

  • Jang, Jung-Shik;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제11권4호
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    • pp.272-277
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    • 2011
  • The ambipolar behavior of tunneling field-effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (${\nu}$). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ${\nu}$.

도핑효과에 의한 L-shaped 터널링 전계효과 트랜지스터의 영향에 대한 연구 (Investigation on the Doping Effects on L-shaped Tunneling Field Effect transistors(L-shaped TFETs))

  • 심언성;안태준;유윤섭
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2016년도 춘계학술대회
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    • pp.450-452
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    • 2016
  • 2차원 TCAD 시뮬레이션을 이용하여 L-shaped 터널링 전계효과 트랜지스터(Tunnel Field-Effect Transistor; TFET)의 도핑농도에 따른 효과를 조사했다. 소스 도핑이 $10^{20}cm^{-3}$ 이상에서 subthreshold swing (SS)이 가장 낮고, 드레인 도핑농도는 $10^{18}cm^{-3}$이하로 하는 것이 음전압에 생기는 누설전류를 막을 수 있다.

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N형 고분자 반도체의 전하주입 특성 향상을 통한 저전압 유기전계효과트랜지스터 특성 연구 (Low-Voltage Operating N-type Organic Field-Effect Transistors by Charge Injection Engineering of Polymer Semiconductors and Bi-Layered Gate Dielectrics)

  • 문지훈;백강준
    • 한국전기전자재료학회논문지
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    • 제30권10호
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    • pp.665-671
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    • 2017
  • Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.