• Journal of Electrical Engineering and Technology
• /
• v.6 no.5
• /
• pp.658-665
• /
• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• Proceedings of the Acoustical Society of Korea Conference
• /
• 1987.11a
• /
• pp.79-81
• /
• 1987

In this paper we propose a fast adaptive least squares algorithm for linear phase FIR filters. The algorithm requires 10m multiplications per data point where m is the filter order. Both linear phase cases with constant phase delay and constant group delay are examined. Simulation results demonstrate that the proeposed algorithm is superior to the LMS gradient algorithm and the averaging scheme used for the modified fast Kalman algorithm.

• 제어로봇시스템학회:학술대회논문집
• /
• 1988.10a
• /
• pp.172-177
• /
• 1988

In this paper, a new fast algorithm of FIR least squares filter with linear phase is presented. The general unknown statistics case is considered, whereby only sample records of the data are available. Taking advantage of the near-to-Toeplitz+Hankel structure of the resulting normal equation, a fast algorithm which gurantees the linear phase constraint, is developed that recursively produces the filter coefficient of linear phase FIR filter for a single block of data.

• Journal of Power Electronics
• /
• v.16 no.4
• /
• pp.1513-1525
• /
• 2016

Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.387-390
• /
• 2012

In this paper, we propose a fast booting solution with embedded linux-based smart devices. We have divided the fast boot process into six steps, such as boot loader, kernel, file system, the init-scripts, shared libraries, and applications for an embedded linux-based boot process to improve the fast booting. Improvements for the fast boot are made in the boot loader phase, which is the first phase at power-up, and the init-script that runs the boot loader phase. To improve the fast booting, standby time from the boot loader and unnecessary initialization routine have been removed, and uncompressed kernel image loading as well as optimized copy routine have been applied. Further, a technology that replaces binary scripts in init-script phase and light-weight init process have been utilized to improve the boot.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1523-1535
• /
• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Korean Journal of Applied Biomechanics
• /
• v.28 no.2
• /
• pp.93-100
• /
• 2018

Objective: The purpose of this study is to analyze the kinematic characteristics of the national speed skaters in the curve phase of 500-m race. Method: Seven national skaters participated in the study. Race images were acquired using a high - speed camera, and the three-dimensional motion was analyzed. Results: For skaters, whose average velocity in the curve phase is high, the velocity of entry into the straight phase was also fast. The fast skaters showed a larger maximum angle of extension of the knee joints than the relatively slow skaters, and the trunk ROM was smaller. Fast skaters tended to match the timing of the movement of the lower limb with the pelvis, while slow skaters tended to rotate the left pelvis backward. The velocity of the curve phase did not show a clear relationship with stroke time, average trunk angle, and lap time. Conclusion: It is important to skate close to the inner line, keep the trunk ROM below 10 degrees, extend the knee angle to over 160 degrees, and match the movement of the pelvis and lower limb to accelerate in the curve phase. The average velocity of the curves was fast for many athletes, but the competition rankings were low. Therefore, it is possible to improve the performance by optimizing the start technique, the running characteristics of the straight phase, and the physical factors.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.582-586
• /
• 2005

This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

• Journal of IKEEE
• /
• v.20 no.3
• /
• pp.314-317
• /
• 2016

Recently, efforts to maximize battery life in progress with an increase in the demand for portable devices. In this paper, we propose multi-phase buck converter with fast transient response. Multi-phase buck converter may be used for the output capacitor of small size because the ripple cancellation effect, it is possible to use an inductor having an inductance less. The portable device for quick change from standby mode to active 4-phase design structure was given a fast transient response. The proposed multi-phase buck converter was fabricated using a 0.18 um CMOS process and the supply voltage ranges from 2.7V to 3.3V, the maximum load current is 500mA and settling time is 10us.

• Proceedings of the Korean Institute Of Construction Engineering and Management
• /
• 2008.11a
• /
• pp.5-12
• /
• 2008

The construction of Pusan National University Yangsan Hospital is a new construction of a medical town in Yangsan. It is a case that CMr participated in the project from planning to post-completion. It shows an actual proof of Construction Management business applied CM by each phase. In this case, CMr selected the design-build contractor in the planning phase and technically performed CM businesses in every single phase such as design and construction schedule management regarding application of Fast Track technique, procurement management and contract administration in phases based on the Fast-tract; technique, design review, VE in the design phase, change order management in the construction phase and operating and maintenance in the post-construction phase. This study would go far toward applying CM to Mega Turnkey projects by analyzing the problems of CMr's practical application to the project and providing guidelines for effective and efficient CM business implementation especially in the Turnkey projects.